Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Safelogic rolls out new property checking solution

Posted: 30 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:safelogic? verifier 2.1? simulator? monitor 3.4?

Safelogic, a developer of PSL-based verification tools, announced a major new release of its property checking solution (Safelogic Verifier 2.1) and extended simulator support for its simulator plug-in product (Safelogic Monitor 3.4).

According to the company, the new Safelogic Verifier product introduces new methodologies that significantly reduce expensive verification time and deliver high verification confidence throughout the design flow. It also provides immediate verification results on a continuous basis, which helps engineers optimize and minimize the verification cycle.

With PSL support, Safelogic Verifier now offers full verification, modeling and safety temporal layer capabilities. Safelogic said that this ensures simple property specification and management, allowing for easy verification of IP and IP re-use.

The property checking solution verifies PSL properties of RTL hardware designs (Verilog and VHDL) and conducts powerful bug finding without test vectors. Its flexible, intuitive user interface allows for seamless integration into existing design and verification environments, delivering full proofs for PSL properties that meet design requirements, and counter-examples where the design fails to meet specified properties. To assist fast and accurate debugging, counter-examples for failed properties are mapped to relevant design signals.

The Safelogic Monitor 3.4

The new and extended release of the Safelogic Monitor product is a simulator plug-in for property simulation. The dynamic property checker is now fully integrated with various simulators, including ModelSim, VCS and NC-Sim and supports VHDL, Verilog, and SystemVerilog as well as mixed-language designs.

The Safelogic Monitor offers an easy step from traditional simulation into property-based verification with the introduction of PSL properties. With it, engineers can track the simulation in real time and are immediately alerted if a property is violated. Combining the power of formal property checking with the strengths of simulator-based dynamic property checking, users benefit from a unique work methodology and are given extensive verification feedback.

The Safelogic Verifier is available on Solaris 8, Windows 2000/XP and Red Hat Linux 7.3, 8.0 and 9, while the Safelogic Monitor is available for ModelSim, NC-Sim and VCS simulators.

Article Comments - Safelogic rolls out new property che...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top