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SONET CMOS transceiver hits 10Gbps

Posted: 01 Jul 2004 ?? ?Print Version ?Bookmark and Share

Keywords:sonnet? cmos? transceiver? optical network? cmu?

We developed a single-chip full-rate 4:1 Serdes consuming less than 1W in a standard 0.13?m CMOS technology. Previous comparable designs were commonly designed in SiGe and BiCMOS technologies.

Also, we devised a special power supply concept to suppress crosstalk between the receiver (Rx) and transmitter (Tx) side of the transceiver. This was done along with a novel high-Q notched inductor that is laid out in the VCOs, and whose phase jitter is five times below SONET specifications.

The XT38702 is a completely integrated transceiver comprising a limiting amplifier, clock and data recovery (CDR), mux/demux and clock-multiplying unit (CMU). No additional external components are needed to operate the device, which features power consumption of <1W.

The input sensitivity of the 10Gbps Serdes is less than 15mV. The transceiver locks automatically to all data rates in the range of 9.95Gbps to 10.7Gbps, making it suitable for most 10Gb applications.

The Tx consists of a CMU and a 4:1 mux, while the Rx comprises a limiting amplifier followed by CDR and a 1:4 demux. No additional external components are required. All high-speed circuitry is realized in differential current-mode logic employing synthetic inductor loads to increase bandwidth. The circuits are powered by per-sub-block linearly regulated supplies, which allow maximum signal swing without exceeding device breakdown voltages.

Rx/Tx crosstalk is minimized through local capacitive coupling of the regulated supplies to a common ground plane, as well as by providing a low-impedance path with as many bond wires as possible to external ground. Since the supply regulators provide isolation of the local supplies from the global one, it is ensured that there is only one low-impedance path from every supply node to external ground. Thus, any undamped LC loops prone to peaking are avoided.

All VCOs share a basic building block and operate at 10GHz. The block consists of a cross-coupled NMOS differential pair providing the necessary negative transconductance, a single-loop horseshoe inductor, a pn-junction varactor and an array of metal-insulator-metal (MIM) capacitors.

Measurements confirmed that inductance increased by 6 percent and in quality factor by 30 percent to a value of 26GHz at 10GHz. The pn-varactors are used for continuous tuning during normal operation of the PLLs. Their tuning range is 300MHz. The MIM capacitors are used to initially calibrate the VCO to a reference clock, achieving an accuracy of 1 percent within a range of 1.2GHz. This produces a wide tuning range and improved phase noise, which is essential for CMU performance. The differential pair is embedded into a deep N-well to avoid substrate crosstalk.

The CMU VCO achieves a phase noise of -118dBc at 1MHz, drawing 6.5mA from a 1.2V supply. By keeping the PLL loop bandwidth constant, designers obtained an optimum flat jitter-transfer function of the CMU. To accomplish this, designers compensated for the nonlinear VCO gain characteristic by adjusting the charge-pump current inversely proportional to it. The full-rate design allowed them to decrease incoming data jitter, as the 4:1 mux is retiming the output data at a full 10GHz. When integrating the device to the requirements of SONET OC-192 specifications, the chip yields a jitter (rms) of 200fs.

The recovered 10Gbps data is fed to a 1:4 demux. The transceiver operates from 9.95Gbps to 10.7Gbps with a bit error rate below 10-12.

- Heinz Werker and Stephan Mechnig

Xignal Technologies AG

With contributions from Christophe Holuigue, Christian Ebner, Frederic Roger & Gerhard Mitteregger

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