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Silterra, IMEC to develop 0.13?m process

Posted: 02 Jul 2004 ?? ?Print Version ?Bookmark and Share

Keywords:silterra malaysia? imec? cmos? communications?

Silterra Malaysia Sdn. Bhd. and the IMEC research center have agreed to create a foundry-compatible 0.13?m CMOS manufacturing process to be based on an IMEC's 0.13?m manufacturing process modified to meet foundry customers' requirements, Silterra said Tuesday (June 29, 2004).

"We are excited about this project because IMEC is well known for its world-class R&D expertise," said Bruce Gray, chief operating officer and interim CEO of Silterra. "We have already completed the groundwork with customers to define their technology requirements, and understand their specifications. Together Silterra and IMEC will take the next steps to develop a compatible 0.13?m technology for the foundry industry."

A team of Silterra and IMEC engineers will fine-tune the basic IMEC process at IMEC's research facility in Leuven, Belgium, to meet Silterra's specifications.

Physical design rules and electrical characteristics will be established to match other mainstream technologies and allow customers to support a multifoundry sourcing strategy. The technology will use fluorosilicate glass or low-k intermetal dielectric options and up to eight layers of copper interconnect.

Silterra did not say whether it intended to make its manufacturing process compatible with foundry industry leaders such as Taiwan Semiconductor Manufacturing Co. Ltd. or United Microelectronics Corp.

"Our 0.13-micron platform technology is a great starting point to build on because it is proven and will help shorten development cycle times significantly," said Gilbert Declerck, IMEC's president and CEO.

The process will target communications, consumer and computational applications. Silterra expects to provide supporting design libraries and IP in the first quarter of 2005, with pilot production starting in the second quarter of 2005.

- Peter Clarke

Silicon Strategies





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