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Tensilica compiler automates RTL generation

Posted: 12 Jul 2004 ?? ?Print Version ?Bookmark and Share

Keywords:rtl block? tensilica? xtensa processor extension synthesis compiler? xpres compiler? xtensa lx embedded processor?

Claiming to provide an increasingly attractive alternative to custom RTL blocks, Tensilica announced its Xtensa Processor Extension Synthesis (XPRES) Compiler. It automatically generates RTL code for Tensilica's Xtensa LX embedded processor from C language algorithms.

Tensilica's Xtensa cores are configurable, extensible and synthesizable 32-bit RISC processor cores. The XPRES Compiler works specifically with the recent Xtensa LX, which adds I/O throughput and computational bandwidth to the earlier Xtensa V processor.

Tensilica has long supported C language design, but it's taken a fair amount of work until now, said Bernie Rosenthal, Tensilica SVP of marketing and sales. Designers have had to profile C algorithms to find slow spots, architect the extension capability of the processor, manually insert "intrinsics" into the code and use the Tensilica Instruction Extension (TIE) language to manually optimize the processor.

"It's a pretty standard toolset for the software developer, but the hardware guys don't know what to do with it because they aren't used to profiling C code," Rosenthal said. "This [XPRES] automates that completely, so you don't have to do any modification to the original algorithm."

In essence, XPRES provides an automated front end to the Xtensa Processor Generator, which produces the actual RTL code for the chosen processor implementation. XPRES compiles unmodified C/C++ code, evaluates thousands or millions of possible extensions, and lets the designer pick the most optimal configuration. Designers can still choose to refine the configuration by using the TIE language.

With the new tool and the more powerful Xtensa LX processor, Tensilica can offer an alternative to hand-coded RTL blocks for a number of data-intensive applications, Rosenthal said. These include video, imaging, audio and encryption applications. Users get an optimized processor for that application, not a coprocessor, he noted. "You can describe just about any algorithm that would go into a piece of RTL and not have a general-purpose processor bottleneck," he said.

While the Xtensa V compels a 10 to 20 percent penalty in area and performance compared to hand-coded RTL blocks, the Xtensa LX brings that penalty "down into the noise," Rosenthal said. He added that power consumption is often better than custom RTL blocks, because of capabilities like fine-grained clock gating.

XPRES is not, however, a C-to-silicon solution. While it automates the production of RTL, designers at that point still enter a traditional ASIC flow and complete the design using synthesis, placement and routing.

Although it performs scheduling and resource allocation, XPRES isn't a general-purpose behavioral synthesis tool, Rosenthal noted. "We're taking a very specific algorithm that can run on a processor and using the processor's capability to accelerate hot spots," he said. "It's not meant for something that can't run in a processor environment."

To use XPRES, designers first compile ANSI C/C++ code for the base Xtensa LX processor unit. This has a lower limit of 25,000 gates, and the upper limit can be "whatever you can close timing on," Rosenthal said.

Next, XPRES comes back with a number of possible configurations, along with a graphical representation of speed and power tradeoffs versus gate count. In one Tensilica benchmark, the tool visited 1.8 million configurations for an MPEG-4 decoder in 30min. The user selects a configuration, and can hand-modify it using TIE.

Finally, XPRES generates the RTL along with a software development tool chain including an instruction-set simulator, debugger, compiler and linker for the customized processor.

The XPRES Compiler will be available in the Q3 starting at $100,000 for a floating license. It requires a separate license for the Xtensa LX processor.

- Richard Goering

EE Times

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