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Consultant creates low-end mixed-signal simulator

Posted: 16 Jul 2004 ?? ?Print Version ?Bookmark and Share

Keywords:usysintegral? xspicehdl? xspice? circuit simulator? georgia technical research institute?

In the middle of a tough design project in 2002, consultant Brendan Graham needed an inexpensive mixed-signal simulation tool. He couldn't find one, so his company, ?SysIntegral, with financial backing from the client, built its own.

Now, ?SysIntegral, is going into beta testing with XSpiceHDL, which links the XSpice circuit simulator from the Georgia Technical Research Institute to commercial Verilog simulators. While it's in beta testing, an unsupported version of XSpiceHDL can be downloaded free from the company's website.

?SysIntegral, the Greek ? character stands for micron, has been doing digital and analog hardware design for more than a decade, said Graham, the company's CTO. Customers include Intel, Texas Instruments, Sky Computer, Veridian and the former Digital Equipment Corp.

But ?SysIntegral has decided to refocus on low-end EDA, Graham said. This decision arose out of Graham's experience with a client in 2002.

"I needed to do some very precise work involving both analog and HDL design, and I did not have a tool on my desktop," he said. "When I went to Mentor and Cadence, I discovered the tools were extremely expensive. I felt that if a tool did not exist on the low end for under $10,000, that there was a market niche for it."

XSpiceHDL is now "fully functional," Graham said, but still in beta testing. "We don't want to charge for it," he said. "When we've finished beta, and we're very sure there are no further bugs, we'll put up a for-sale sign." Pricing has not been set.

The tool does not include a Verilog simulator, though one is planned. It does, however, provide dynamic link libraries that let users link in their Verilog simulators through a programming language interface or Verilog programming interface. Currently, the tool supports Mentor Graphics' ModelSim and Cadence Design Systems' Verilog-NC and Verilog-XL simulators, in addition to the Icarus open-source Verilog simulator. Support for Synopsys' VCS simulator is coming soon, Graham said.

XSpice is an enhanced version of Spice that's event-driven. Thus, it permits mixed-signal simulation, but the public-domain version of XSpice is limited, Graham said. For one thing, it relies on manual input of digital netlists as graphical symbols.

"If you try to execute [XSpice] 3f5 [simulator] with schematic capture, entering any quantity of digital circuitry would be excruciatingly painful," Graham said. "So, we provided an interface to Verilog that allows you to do an HDL description, and then do your analog description in Spice on a GUI that we provide. Then you hit the 'go' button, and the HDL will interface with the Spice netlist."

XSpiceHDL includes the XSpice 3f5 engine, but it adds proprietary algorithms, code models and enhanced XSpice engine. XSpice includes code models for components such as A/D converters, multipliers, integrators, S-domain transfer functions and digital gates. XSpiceHDL adds code model libraries for devices such as digital FIR and IIR filters, adaptive LMS filters, adaptive echo cancellers and equalizers, de-convolution filters and other DSP functions. Most notably, the enhanced code model library includes ?SysIntegral's SocketNode protocol converter, which provides the communications channel and protocol through which the XSpice engine works with Verilog.

Graham explained that the master clock is controlled from XSpice. An arbitrary number of socket clients are instantiated on the XSpice side, and a similar number of socket servers are instantiated on the Verilog side. The simulators are synchronized through the clients, and the Verilog simulator can't run ahead of XSpice.

XSpiceHDL uses an asynchronous handshaking arbitration algorithm and protocol to allow one or more XSpice engines to co-simulate with one or more Verilog engines. Later, Graham said, ?SysIntegral will add support for VHDL, MathCAD and SystemC simulators.

XSpiceHDL also uses dynamic CPU load balancing to enable co-simulation speed and throughput when two or more simulation engines are executing concurrently on a single CPU. A platform-independent product, XSpiceHDL can be compiled for Unix, Linux or Windows.

Graham said he expects XSpiceHDL to spend another three months in beta testing.

- Richard Goering

EE Times

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