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Synopsys chief takes fab vendors to task

Posted: 20 Jul 2004 ?? ?Print Version ?Bookmark and Share

Keywords:eda? 130nm? ic? fabrication tool?

The chief executive of EDA industry leader Synopsys Inc. told a chip industry conference that the emerging design-for-manufacturing approach is a two-way street and that the two industry segments must find ways to collaborate.

Synopsys CEO Aart de Geus told the Semicon West conference here, "After 130nm, everything has changed and we can no longer throw designs over the wall and expect them to be fabricated at acceptable yields."

de Geus called for fabrication tool vendors to restrict the number of new design rules before chip designs can be sent to the fab and manufactured on schedule. "It is as much a design-for-manufacturing paradigm as it is a manufacturing-to-design idea that needs to be made effective," said de Geus.

Below 130nm, there are too many variables for design and manufacturing to remain independent. While some progress has been made in exchanging common data, closer collaboration is still needed, he added.

The design and fabrication communities need to find "yield recipes" that would determine how design affects yield at each step of the design process. The recipes would look ahead in the process, readjusting it as the initial idea for a new IC is translated into a finished chip.

"We were great at moving down the technology nodes from 250 to 200 to 180, but at 130nm we were very surprised to see yields in the 13 percentile instead the normal 90 percent we were used to," explained de Geus. "We must anticipate growing complexity at each step of the design-to-manufacturing process."

Clever engineering keeps saving the day. "We underestimated the side effects of using copper as an interconnect metal," said de Geus. When chemical metal polishing led to "dishing" of the surface, the problem was solved by inserting dummy fills and metal slots.

Another problem is via reliability. Though solutions are being implemented to make chips work, "it is still much a guessing game as to what the next solution needs to be." He called "design intent" the barometer for anticipating potential problems at each and adjusting the process well ahead of tapeout.

The Synopsys executive said a form of automatic diagnosis needs to be inserted into the design process. It could serve as a catalyst to readjust the process and avoid failures. "We are already starting to use this technology."

Design starts are slipping, de Geus said, and renewed growth will require eliminating uncertainty so that the completed chip works the first time according to specifications.

The next hurdle is leakage. As of May there were 194 90nm design starts in the works, according to de Geus. "Their chance of seeing volume [production is] diminished if leakage can not be engineered out."

That, said de Geus, is another reason collaboration is needed early in the design stage.

- Nicolas Mokhoff

EE Times

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