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VIA highlights design challenges at 90nm

Posted: 28 Jul 2004 ?? ?Print Version ?Bookmark and Share

Keywords:ic design? via technologies? 90nm? 65nm? eda&t-taiwan?

The escalating design costs and complexities have been the greatest challenges for the small and medium sized IC design houses when migrating to deep submicron technologies. Shrinking process geometries increase the difficulty of dealing with power and process variations.

As most design engineers in Asia migrate to technologies smaller than 0.35?m, VIA Technologies' VP of Mfg & Product Eng., Shelton Lu, recommends the more mature 0.13?m process rather than a jump to 90nm or 65nm. Lu was speaking at the forum on "Understanding the next phase of Taiwan's IC design roadmap," held on the first day of the EDA & Test - Taiwan (EDA&T-Taiwan) conference and exhibition in Hsinchu. Participating companies, including VIA Technologies, Socle Technology, Synopsys and Etron Technology, discussed the challenges ahead the design engineering community in Taiwan as well as solutions that are being explored.

"At the 90nm and 65nm nodes, the oxide thickness can get as low as 11 Angstrom, and while there is not much impact on the saturation current, the leakage current increases dramatically," said Lu. "And don't forget that you also reduce the space between interconnects at these nodes. The net result: issues with interconnect parasitic, jitter, clock tree optimization, timing closure, increased operating voltage range and leakage sensitive circuits. You might even be dealing with multiple gate-oxide thicknesses that complicate an already challenging design. You might introduce new faults, including delay faults and transition faults [since the leakage current becomes close to saturation current, it becomes difficult to tell whether a transistor is ON or OFF.]"

While advances in materials will continue to be made, Lu highlighted the urgency to focus on signal-integrity analysis EDA tools, built-in self-test (BIST) of high-speed SERDES I/O for jitter measurement and injection and the development of new fault models.

The 130nm, however, offers a more immediate solution, according to Lu. "There is a wide variety of intellectual property at the 130nm node, which is a significant advantage for those designing highly integrated and complex chips like SoCs," Lu explained. "This node currently offers the best in way of a trade-off between performance/size advantages and design and production difficulties."

- Vivek Nanda

Electronics Engineering Times- Asia

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