Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

Testing SoC interconnects using boundary scan

Posted: 02 Aug 2004 ?? ?Print Version ?Bookmark and Share

Keywords:boundary scan? soc? interconnect? ate? jtag?

Delay violations occurring in the interconnects of high-speed SoCs can be tested using JTAG boundary scan architecture.

View the PDF document for more information.

Article Comments - Testing SoC interconnects using boun...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top