Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Timing closure: Hybrid optimization to the rescue

Posted: 16 Aug 2004 ?? ?Print Version ?Bookmark and Share

Keywords:timing? closure? hybrid? optimization? asic?

Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure.

View the PDF document for more information.

Article Comments - Timing closure: Hybrid optimization ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top