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FPGAs adapt to suit low-power demands

Posted: 16 Aug 2004 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? power? sram? flash? memory?

The right FPGA technology and architecture can help designers reduce power consumption. Thanks to recent architectural advances that address power concerns in FPGAs, it may be time for designers to take another look at the devices as a design option.

Any consideration of FPGAs should start with a look at their fundamental technology, which provides an array of gates, combinatorial logic and registers along with a configurable interconnection matrix so that implementing a design involves activating the right interconnections. The devices capture the configuration using one of three approaches: SRAM, flash memory or antifuse programming. Each has its advantages and limitations for system design.

The SRAM and flash approaches both use a memory-based configuration, with the general structure of a memory-based FPGA calling for a memory cell to control a transistor at a crossover point on the interconnect matrix. The cell can be programmed either to make or to prevent a connection at the crossover point, so configuring the device is a matter of storing the interconnect information into that cell.

The memory-based FPGAs are reprogrammable: If a design needs to be changed, all the designer has to do is provide a new pattern for memory. In many cases, that means a design can be altered even after fabrication, thereby providing ultimate design flexibility.

Volatile memory

The SRAM approach's drawback is that the configuration memory is volatile: If power is lost, so is the configuration. SRAM FPGAs must therefore include a nonvolatile configuration memory that the system can use to program the FPGA during bootup. But this has a further disadvantage: SRAM-based FPGA designs cannot power up quickly, because they must be programmed before they can perform their intended function. Power-up can take several hundred milliseconds.

The other memory-based approach to FPGAs resolves this problem by using flash memory to store the configuration data. The flash cell is nonvolatile yet reprogrammable, avoiding both drawbacks of the SRAM approach while retaining the flexibility. The trouble with flash technology is that the technology is inherently slower than SRAM cells, limiting system performance.

Antifuse option

The third FPGA approach, the antifuse configuration, is also nonvolatile. This approach places a bridge of fusible material at each interconnect crossover site. The via bridge is normally nonconducting. The application of a programming voltage fuses the material of the via into a permanent conductive pathway, thereby making a low-impedance connection where desired. But the device configuration is not reprogrammable; configuring an antifuse FPGA hardwires the design into the device.

All three approaches have evolved to address capacity limitations that have locked FPGAs out of many designs. For example, all FPGA types can now handle designs of several hundred thousand gates, enough to implement a microprocessor with several peripherals in a single component. Also, newer FPGAs offer blocks of uncommitted SRAM that can be used for processor memory. Some also offer computational blocks that allow the FPGA to efficiently implement DSP functions with good performance.

Power is another longtime limitation that newer FPGA designs are addressing. For instance, standby current accounts for most of the battery drain in a handheld device's normal use, so it has a significant impact on battery lifetime for such products. Some FPGA architectures provide designers a way to lower the standby current by powering the I/O section separately.

Shrinking process technologies have long dictated that semiconductor devices run at fewer than 2V, while I/O standardization has remained standard at 3.3V. Typically, devices have an internal charge pump to create the I/O interface voltage, but running a charge pump is an inefficient use of power. By giving designers the option of supplying the I/O power from an external source, newer FPGAs let designers disable the charge pump and eliminate its associated power draw.

Other standby power concerns are not so easily dealt with. For instance, to achieve high density, memory-based FPGAs use 90nm process technology. This process has a greater transistor leakage than prior technologies, drawing current even when the circuits are not clocking. Both the logic and the interconnect memory of these FPGAs suffer from the increased leakage, raising the device's standby current.

Technology choice controls this concern. The small footprint of the antifuse allows these FPGAs to achieve high density without needing 90nm technology, so they can use a process that has less leakage. They also need less standby current in general because they do not need active transistors to maintain device configuration; programming the antifuse causes a physical change that needs no power to maintain.

While standby current is important for battery-powered designs, operating current affects all designs. Fortunately, designers can take steps to reduce a design's average operating current regardless of process technology. FPGA product lines have evolved, improving their architectures to give designers some tools for reducing average power. One major improvement has been to change the internal clocking structure.

Quadrant clocking

Instead of a single clocking tree that covers the chip, some FPGAs now use quadrant-based clocking, a clock distribution structure that gives independent clocks to FPGA segments. It allows designs to be partitioned using gated clocks, so that a segment can be put into a slow clock or a suspended state to save power when its function is not active. The ability to stop clocking unused segments is especially valuable in designs where only a portion of the system must be continually active and the rest used only on demand. For example, a device can halt its processor until a key press or other I/O event signals the need for it to perform some function.

For systems where the triggering results from a human action, the power savings can be tremendous. Human interaction intervals are no faster than milliseconds, whereas the device can complete its task in microseconds. Most of the system's time, therefore, is spent waiting for a human action. Gated clocks allow suspension of all functions but the human interfaces during that wait time, saving considerable power.

Even more power can be saved if the entire device can be shut down when not in use because standby and leakage current draw are eliminated as well.

Device shutdown is not practical with SRAM-based FPGAs; those devices must maintain power in order to retain their configuration, and they take too long to reload to make shutdown down a power-efficient choice. But nonvolatile FPGAs have an instantaneous response to the return of power. Shutting them down results in overall power savings even if the shutdown period is relatively short.

Because the architecture of newer FPGAs supports the use of such power-saving techniques, they are challenging ASICs for power efficiency.

- Mao Wang

Applications Engineering Manager

QuickLogic Corp.





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