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European alliance grows for 45nm gate stack push

Posted: 19 Aug 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cmos? information technologies? 300mm? freescale semiconductor? philips?

Collaborative research is cranking up in Europe, as France's CEA Laboratory of Electronics and Information Technologies (LETI) has gathered partners in a project to develop a 45nm-and-beyond CMOS gate stack with a high-k insulator and metal gate electrodes.

The partnership is based at the French Atomic Energy Commission's (CEA) LETI's new 300mm research facility here called Nanotec 300.

Tokyo Electron Ltd, the world's second-largest equipment company, recently signed an agreement to participate in Nanotec 300, joining the three partners of the Crolles, France, process development alliance: Freescale Semiconductor, Philips and STMicroelectronics.

Under the terms of the deal, Tokyo Electron is to provide its Telformula batch thermal-processing system and its single-wafer Trias system. In addition to the basic development of high-k and metal gate materials, the joint development program also will address pre- and post-deposition processes. "We expect to advance quickly to an integrated customer solution for advanced high-k, metal gate stack," said Peter Horii, a Tokyo Electron VP.

Research plans

The collaboration positions CEA LETI "to propose new 300mm cutting-edge module integration technology to its collaborative partners," said Olivier Demolliens, Nanotec 300 manager at CEA LETI.

The agreement with the Crolles alliance partners covers the development of 45nm, 32nm and more-advanced manufacturing processes by CEA LETI's laboratory. The effort is supported by $350 million in funding, the CEA said.

The plan to create Nanotec 300 was announced in May 2002. Two years later the Nanotec 300 facility was inaugurated, with a 1,000-square-meter clean room and an extensive range of equipment. The research fab is supported by a total investment of about $350 million, from the members of the Crolles2 Alliance, the French government, and regional and city authorities.

The research activities at Nanotec 300 will be divided into patterning, devices, front-end materials and process steps, and interconnect materials and process steps. These programs will be carried out in conjunction with the three Crolles2 Alliance members and their research partners, including IMEC and Freescale Semiconductor's Dan Noble Center.

The Nanotec agreement extends previous CMOS research programs on 200mm wafers between CEA LETI and STMicroelectronics in the Grenoble area. It is also likely to be strongly aligned to Europe's NanoCMOS project and the work being done by the Crolles2 Alliance.

The NanoCMOS project, organized by the European Commission Information Society Technologies agency, is researching the 45nm CMOS logic-manufacturing process node and anticipates the first developments of the 32nm node, said Guillermo Bomchil, a manager at STMicroelectronics who is the NanoCMOS project leader.

The NanoCMOS project has been divided into two phases, with about $32 million allocated for the period extending through mid-2005. For the second phase, the participating organizations are expected to effectively double the first-phase budget to about $64 million.

- Peter Clarke

EE Times





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