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SolarFlare's analog front end taps high-end ADCs

Posted: 30 Aug 2004 ?? ?Print Version ?Bookmark and Share

Keywords:solarflare communications? analog front end? afe chip? adc?

Startup SolarFlare Communications Inc. has completed a high-performance integrated analog front end for handling 10Gb transmission over copper lines. But plenty of work remains on the IEEE's 10GBase-T standard, and products are not expected to be ready for at least another year.

The AFE chip from SolarFlare integrates four 10-bit, 1Gsps ADCs (a dedicated A/D for each wire in a Category 5e Ethernet cable). The chip also sports a dedicated programmable gain amp and PLL for each A/D. A master PLL on the chip synchronizes traffic between each converter.

The company used trench isolation and other noise mitigation techniques in the design. It also conducted significant 3-D model simulation on both the die and its 23-by-23mm, 473-lead BGA package.

The AFE is made in 180nm CMOS, includes 2.7 million transistors and consumes 5W. "This is the only quad 10-bit gigasample A/D I know with this kind of performance and made in CMOS," said Ron Cates, SolarFlare's VP for marketing.

Previously, SolarFlare used four separate 10-bit gigasample ADCs from Atmel Corp. as part of a demonstration board transmitting 10GbE over 50m of Category 5e copper. Using the new AFE the demo transmits 10Gb signals about 70m over Category 6 cable.

To hit its goal of full 100m-transmissions, SolarFlare plans to respin its 130nm custom DSP transceiver in a 90nm process, adding new noise isolation techniques and other features being discussed in the IEEE 802.3an task force developing the 10GBase-T spec.

Cates said SolarFlare could have a product ready to roll by late 2005 based on the 90nm DSP and the current AFE.

Bob Pease, staff chief scientist for data conversion systems at National Semiconductor Corp., said the SolarFlare AFE does appear to hit a milestone in high-performance, integrated ADCs. But he questioned whether the chip might be too expensive and run too hot for significant commercial use.

Pease said that National now ships 8-bit gigasample ADCs that typically consume <1W.

"We will still be able to undercut the cost of [10-Gbit Ethernet over] optical modules by a factor of two at least," said Cates. The cost savings will be even more dramatic once vendors move products to the 65nm node when the DSP transceivers and analog portions could be moved into a single chip, he added.

Standards update

Cates and others said the IEEE 802.3an task force made significant progress at its July meeting and could agree on a first draft of the standard at a late September meeting in Ottawa. At the July meeting, held in Portland, Oregon, the group unanimously approved three key aspects of the 10GBase-T standard. It will use pulse amplitude modulation (PAM); programmable Tomlinson-Harashima precoding, for channel equalization; and low-density parity checking as the channel-coding approach, said Juan Jover, co-founder of Phyten, another startup taking an active role in the standards effort.

"The biggest controversy now is over the line code-whether it will be PAM-8 or PAM-12. That will determine the baud rate of the system. Every day there is more simulation and debate on the reflector about which is better," said Cates.

Phyten, an early-stage startup still in stealth mode, is proposing a PAM-8 approach. Another startup, Teranetics, working with NEC, is proposing PAM-12. SolarFlare and Broadcom Corp. are said to believe the distinction between the two is relatively academic. A final decision could come at the September meeting.

- Rick Merritt

EE Times





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