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Synopsys CEO calls for DFM cooperation

Posted: 01 Sep 2004 ?? ?Print Version ?Bookmark and Share

Keywords:gdsii? fabrication? manufacturing? dfm? fab?

Aart de Geus has added his influential voice to the design-for-manufacturing (DFM) discourse. During a keynote address at Semicon West, the Synopsys Inc. chairman and CEO called on the design and fabrication communities to develop "yield recipes" that would provide insight, at each step of the design process, into how design ultimately affects yield.

Seizing his first opportunity to address the conference, de Geus told his audience of semiconductor manufacturing tool providers that DFM is a two-way street. "After 130nm, everything has changed," he said. "We can no longer throw designs over the wall and expect them to be fabricated at acceptable yield."

By the same token, de Geus called for fabrication tool vendors to restrict the number of new design rules that are thrown back to the design community. "It is as much a DFM paradigm as it is a manufacturing-to-design idea that needs to be made effective," he said.

After the 130nm node, de Geus said, too many variables came into play for design and manufacturing to remain independent endeavors. While some progress has been made to exchange common data sets, each side is still holding too much critical information too close to the vest, he said.

He called for cooperatively developed yield recipes that could look ahead and adjust the design process accordingly as the initial idea for an IC design is translated into a finished chip. "We were great at moving down the technology nodes from 250 to 200 to 180," he said, "but at 130nm we were very surprised to see yields in the 13th percentile instead the normal 90 percent. We must anticipate growing complexity at each step of the design-to-manufacturing process."

Thus far, clever engineering has managed continually to save the day. For example, "As an industry, we underestimated the side effects of using copper as an interconnect metal," said de Geus. When chemical metal polishing led to "dishing" of wafer surfaces, the problem was solved by inserting dummy fills and metal slots. Another problem addressed by engineering feats has been via reliability.

While solutions are being implemented that make complex chips work, "it's still a guessing game as to what the next solution needs to be," de Geus said. He called for "design intent" as the barometer for anticipating problems at each design stage and adjusting the process long before tapeout.

Some sort of automatic diagnosis needs to be inserted into the design process that would be the catalyst for adjusting the process to avoid failures, de Geus said. "In fact, we are already starting to use this technology," he said.

The Synopsys CEO pleaded with capital equipment vendors to stop adding new design rules with each adjustment of their latest fab tools--a process that he said leads to more complexity and forces design tool vendors to change their algorithms on the fly. "We need to work together so that we can accelerate production ramps by months and achieve automatic diagnosis of problems in hours, not days," he said.

The number of design starts is slipping, he warned, adding that the trend will be reversed only if designers can eliminate uncertainties and be assured that the final chip will work correctly, according to specification, the first time it is implemented in silicon.

In what he called the "decade of the consumer," de Geus said leakage current is the next crisis. "Synopsys can track design starts worldwide, and as of May there were 194 90nm design starts in the works," he said. "Their chance of seeing volume is diminished if leakage cannot be engineered out."

Sandeep Khanna, marketing VP for DFM at Synopsys, said the market for DFM EDA tools was about $140 million in 2003, with projections for about $180 million in 2004 and $390 million in 2007. Tools for mask synthesis and data preparation, as well as mask writing and inspection, will contribute to DFM market growth, Khanna said. "There needs to be a holistic approach across process and design," he added.

In the past, little design manipulation had been required around the task of mask writing, Khanna said. But with the move to subwavelength lithography, a number of resolution enhancement techniques were added at the same time that design complexity was increasing exponentially. The time spent manipulating multilayer data to create appropriate mask sets has contributed to the increasing cost of mask sets and the importance of getting them correct, Khanna shared. It has also led to other categories of software for mask verification.

"The move from 130nm to 65nm could result in 20 to 30 times the resolution enhancement technique (RET) complexity as other variables come into play in mask making," he said.

Claiming to be creating a winning position in DFM EDA tools, Synopsys has chosen to persevere with the venerable GDSII IC layout format until first-half 2005, rather than adopt the more compact Oasis layout format created in 2003.

Rival Mentor Graphics Corp. already has tools in its Calibre suite that can work with either the GDSII or Oasis formats. But observers said that until physical synthesis tools start producing IC layout files in the Oasis format as a matter of course, engineers will continue to think of GDSII as the standard. Mentor has announced a free downloadable GDSII-to-Oasis layout translator in an attempt to kick-start use of the latter format.

Khanna said Synopsys expects to introduce Oasis-capable tools "in the first half of 2005. It will take some time to upgrade the tools; it can't happen overnight."

- Nicolas Mokhoff and Peter Clarke

EE Times

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