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Understanding passive channel

Posted: 01 Sep 2004 ?? ?Print Version ?Bookmark and Share

Keywords:channel? backplane? line card? switch? serdes?

As the industry tackles the standardization of high-speed serial data transmission for 10Gbps and beyond, it is imperative that engineers fully understand the passive channel. Proposed solutions that focus on the active-component level over channels that are not representative of real commercial products will not do it.

The toughest obstacle is agreeing on the needs of the passive channel vis-a-vis the needs of the overall system. For example, demonstrating a working 10Gb solution where the line cards and backplane are made from Rogers 4350 is not practical for an enterprise application, where pricing pressure is intense.

Improvements in active components have provided a more cost-effective solution from a system level. But the performance and cost of the passive aspects of the channel have not improved at the same pace. Gains are limited by their associated cost and manufacturability, as well as the physical realities of system architectures. Further, the differing performance and cost requirements of the carrier and enterprise markets dictate whether these improvements can be used.

The bandwidth capacity of the passive channel is limited by trace skin-effect losses, dielectric losses and resonant structures. All directly influence the scope of the problem and the choice of solution.

Some believe that efforts to standardize serial 10Gb transmission should focus on so-called green-field backplanes that use improved board materials, connectors, stub removal techniques or overall architecture. Such backplanes will enable higher channel capacities, allowing the use of active components that meet the market's requirements for die real estate, power, thermal and cost.

Others favor legacy backplanes. System vendors want to enable the use of backplanes now in the field, as it is imperative that they prevent forklift upgrades for their installed customer base.

Both views are supported by powerful arguments. While it is reasonable to assume the channel performance of green-field backplanes will improve, this expectation must be tempered by the OEM cost structures that include manufacturability and product reliability. These will ultimately limit the amount of improvement in channel capacity.

In terms of trace dimension--which includes trace width and length--the backplane presents interesting challenges directly related to the architecture of the system. The maximum length of backplane traces may vary from a few inches for a midplane application to 20 inches to 30 inches for typical backplane applications.

For example, in a switch architecture, the switch slots are typically located in the center of the backplane. This helps minimize the overall trace length. In terms of routing, the area near the switch slots will be heavily congested and ultimately determine the number of signal layers required.

In the full-mesh architecture, with no centralized switching function, all blades supporting the data plane will be interconnected. This will help reduce centralized areas of trace congestion, but increase trace length. Further, the aspect ratio of vias in the board will limit the overall board thickness. Aspect ratio and board thickness constraints combined with the required number of signal, power and ground layers will ultimately determine the maximum allowable trace width.

Line and fabric cards also have an impact on channel capacity. Consider whether an ASIC with integrated or discrete Serdes is used. The latter option increases flexibility in placement, which helps reduce overall trace length. The use of an ASIC with integrated Serdes devices helps to reduce overall cost and power.

The path length from the ASIC to the connector will grow. Trace lengths of 6 inches to 10 inches are common. The increase in length combines with the fact that wide traces used to meet impedance and thickness constraints cannot be tolerated on cards. Loss will rise rapidly with frequency in a channel that must include 20 inches of 4- or 5-mil-wide traces.

Newer dielectric materials can offset this loss. However, the typical cost of these materials is twice or more that of a design based on FR-4. Costs of qualifying such materials can be considerable as well.

Perhaps combining stub removal with surface-mount connectors will enable higher channel capacities than with press-fit connectors. Engineers must consider layer construction, material selection, hole size and trace width when determining a stub removal technique.

- John D'Ambrosia

Manager of Semiconductor Relations

Tyco Electronics Ltd

- Joel Goergen

Chief Scientist

Force10 Networks Inc.

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