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Cadence emphasizes solutions in design tech symposium

Posted: 03 Sep 2004 ?? ?Print Version ?Bookmark and Share

Keywords:elctronics design software? cadence design systems? Virtuoso? allegro? incisive?

As part of a promotional campaign of its portfolio in Southeast Asia, Cadence Design Systems showcased different versions of its electronics design software solutions in a design technology symposium held in Manila, Philippines in Aug. 24.

The symposium consisted of three parallel platform breakout sessions featuring Cadence's design software solutions, such as the Virtuoso custom design platform, the Allegro system interconnect design platform and the Incisive verification design platform.

Virtuoso platform

The Virtuoso custom design platform highlights what Cadence calls the "meet-in-the-middle" methodology that merges the speed of the top-down design with the silicon accuracy of the bottom-up design. Virtuoso delivers capabilities, such as multimode simulation (SPICE, RF, AMS and FastSPICE), specification-driven environment, transistor-level silicon and full-chip integration analysis, and layout optimization and migration.

Virtuoso includes multimode simulation UltraSim, a 3G hierarchical, isomorphic simulator with silicon accurate models utilizing speed-up techniques including partitioning the design into smaller matrices and event-driven and multirate simulation; and a specification-driven environment which can double the productivity rate and cut the verification time into half with its thorough characterization.

Allegro/Incisive platforms

System interconnect co-design platform Allegro aids from the silicon, to IC, to packaging stages by enabling collaboration between IC companies and customers in designing high-performance interconnects, reducing costs due to hardware re-spins and speeding up time-to-market. The Allegro system interconnect platform looks forward for impending challenges such as multi-GHz interconnect design and system-in-package co-design.

Allegro underscores the need for a 3D field solver due to system demands such as increased signal speed, reduced edge rate and geometry, high-density pin count packages and complex power delivery schemes. Paksi-E is chosen to deliver handling of complicated 3D structures in a wide frequency range.

Employing a single-kernel architecture, Incisive verification platform fuses multiple verification techniques in one engine to overcome fragmentation, which packs total verification time to 50 percent. Cadence partners with CoWare to deliver integration and reduced time-to-market benefits to customers.

The symposium is part of Cadence's strategy to increase its reach in Asia particularly in China where the IC design industry is rapidly growing. The design industry in Southeast Asia is also important, according to SP Ng, managing director for South Asia operations at Cadence.

Supporting the EDA industry in Southeast Asia is equally important and the timing is right. "The EDA industry in this region is very young," said SP Ng. He expressed that as much as countries concentrate in the manufacturing sector, the design arm ought not to be left out. With China becoming a powerhouse in manufacturing, other Asian neighbors should consider other areas in the value chain including IC or system design.

Several engineers from different semiconductor and electronics firms and people from the academe were present in the event. Semiconductor and Electronics Industries in the Philippines Inc. (SEIPI) Executive Director Ernie Santiago keynoted the event as he shared insights on the state of the local electronics industry. Laurence Tan, general manager for South Asia operations in Cadence, also presented a corporate overview.

- Reden Mateo

Electronic Engineering Times- Asia





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