Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Cadence, UMC create sub-130nm IC reference flow

Posted: 10 Sep 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cadence? umc? 130nm? digital ic design? an rtl-to gdsii reference flow?

Cadence Design Systems Inc. and foundry United Microelectronics Corp. have announced an RTL-to GDSII reference flow for digital IC designs implemented in UMC's 130nm and lower processes.

The reference flow incorporates Cadence technologies, including Encounter RTL Compiler, First Encounter GPS (Global Physical Synthesis), NanoRoute, Fire & Ice QX, CeltIC-NDC, VoltageStorm power analysis and Assura physical verification Tools, the companies said. The flow uses a "wires first" methodology to address key nanometer design issues such as timing closure, signal integrity and power integrity.

The Cadence-UMC flow also uses Faraday Corp.'s library and memories.

The UMC and Cadence digital reference flow kit is currently available at no charge to UMC customers, from UMC sales representatives or accessible online through UMC's Web site.

- Mike Santarini

EE Times





Article Comments - Cadence, UMC create sub-130nm IC ref...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top