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Synplicity upgrades FPGA logic, physical synthesis tools

Posted: 17 Sep 2004 ?? ?Print Version ?Bookmark and Share

Keywords:synplicity? fpga? synthesis tool? xilinx? lattice semiconductor?

Synplicity Inc. has announced the latest version of its FPGA logic synthesis and physical synthesis software solutions featuring what it claims is better quality of results and performance than the previous version. The tools also support the latest device families from Xilinx and Lattice Semiconductor.

According to the company, its Synplify Pro 7.7 synthesis tool features timing-driven synthesis support for Xilinx's Virtex-4 FPGAs and support for Lattice Semiconductor's LatticeECP and LatticeEC low-cost FPGA device families.

The Virtex-4 improvements also offering reduced area (cost) optimization once timing performance goals are met, the company said. Synplicity also made timing closure improvements to its Amplify FPGA 3.7 physical to improve timing for high-performance FPGAs.

The Synplify Pro software also features enhanced mapping technology for Lattice Semiconductor's new LatticeECP and LatticeEC FPGAs, Synplicity said.

New arithmetic function generators built into the Synplify and Synplify Pro products aim to provide DSP designers improved timing performance for math-intensive applications. The feature allows Lattice users to take advantage of the LatticeECP-DSP's dedicated multiplier/accumulator DSP. The latest version of the Amplify FPGA physical synthesis software includes improved timing correlation to final place and route, as well as a new island-based timing report that allows designers to view and constrain all physically-connected paths in designs that have negative slack.

The feature, the company said, should allow users to perform fewer place-and-route iterations. When combined with the software's improved timing correlation algorithms, the island-based timing report also permits designers to meet aggressive timing goals quickly. Synplicity said it has also integrated its Identify Instrumentor product into Synplify Pro v7.7 software, providing easier access to RTL instrumentation and debug capabilities.

Identify software allows FPGA designers and ASIC prototype designers to functionally debug their hardware directly in their RTL source code.

The Identify software is intended to help designers pinpoint problems in their Verilog or VHDL code, saving weeks in design time.

Through the end of 2004, customers in North America who purchase a new license will receive the Identify RTL Debugger free of charge for use with Synplify Pro.

Pricing for the Synplify software starts at $9,500 and pricing for the Amplify Physical Optimizer software starts at $29,000.

- Mike Santarini

EE Times





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