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Samsung methodology reduces SoC design time

Posted: 21 Sep 2004 ?? ?Print Version ?Bookmark and Share

Keywords:samsung electronics? co-design methodology? soc? virtual platform? vip?

Samsung Electronics Co. Ltd revealed a hardware/software co-design methodology that it claims will reduce overall design time for the company's SoC products by up to 40 percent. The new Virtual Platform (ViP) approach will ultimately result in faster production of their logic components while giving their customers a time-to-market advantage, the company added.

Samsung developed the ViP design methodology in partnership with EDA vendors to address the ever increasing complexity of SoC design challenges. "The ViP methodology has improved system design productivity and reduced SoC design and software development cycles," shared Soo-kwan Eo, who leads the ViP development team and is the SVP of Samsung's SoC R&D Center. "ViP will help us develop highly integrated devices ahead of the competition to maintain our market leadership."

Using the ViP methodology, simulation speeds are hundreds or even thousands of times faster than that of a traditional RTL approach while maintaining more than 90 percent of accuracy over RTL, Samsung claims.

The company also said that some of its SoC products have already benefited from the ViP methodology. It has been applied to develop the flash memory card controller that is already in mass production, enabling engineers to improve certain chip performance such as the data read operation by more than 30 percent, Samsung remarked.

The company's ViP design methodology has proven its applicability to its SoC products with multiple processors. It plans to expand the use of ViP within its logic product line to encompass other various SoC devices.

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