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Synthesis suite targets unconventional designs

Posted: 01 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:ftl systems? eda? merlin? tool suite? behavioral synthesis?

FTL Systems Inc. is quietly preparing a complete IC design solution, but this small, privately held company isn't about to go head-to-head against the big EDA vendors. Instead, the company said it is focusing on problems that conventional EDA tools can't solvemost notably ICs are that asynchronous or require radiation hardening or have huge gate counts.

FTL Systems is engaged in early releases of Merlin, a tool suite that includes behavioral synthesis from VHDL or SystemVerilog; analog synthesis from VHDL-AMS or Verilog-AMS; and analysis and simulation. It outputs placed netlists, and FTL plans to add a complete placement, routing and extraction capability.

Merlin almost sounds like a wizard's tool. In addition to handling any logic technology, including asynchronous designs, the company said the tool can synthesize or simulate 100Mgate-equivalent designs with no partitioning, while running in parallel on workstations with up to 128 CPUs.

FTL Systems is not a startup armed with vaporware. Founded in 1995, the company has been developing and selling its parallel compilation and simulation technology for nearly 10 years.

Merlin's user interface is simple. There are three windowsa design view, a model view and an implementation view. Each has 10 to 25 tabs, each representing a point tool. For example, the design view includes a tab for a source-code editor. The model view includes a simulator, waveform viewer, spectral analysis tool and power analyzer. The implementation view includes behavioral synthesis, analog synthesis, simulation and formal verification.

What really makes Merlin unique, Willis said, is its ability to work with different logic technologies. "With other synthesis tools, a lot of the understanding of the technology that's being targeted is hardwired into the tool," he said. "You really can't apply a new coding theory."

This means that users can customize Merlin to target a logic technology of choice, such as asynchronous logic. That's happening at Theseus Logic Inc., a developer of clockless IC technology.

"Every time they come up with a new way to implement an adder or a handshaking protocol, all of the control to implement that technology is at their disposal," Willis said. "There's no need for them to call us. Previously, they had to write scripts around Synopsys tools, because they couldn't change the internals."

Designers target specialized logic technologies with dynamic-link libraries (DLLs). It's analogous to the way the GNU C compiler can go from one target machine architecture to another, Willis said. "If somebody wants a rad-hard methodology, they can get a DLL from a company that specializes in rad-hard coding for single events."

Capacity is another differentiator for Merlin. Willis said the product was able to synthesize a 100Mgate equivalent design without partitioning, on a single Sun Microsystems Inc. workstation with 30 to 60 CPUs and 100GB of memory. Each 10Mgate to 20Mgate equivalent takes about 4GB of memory, he said.

One drawback for ASIC designs, however, is that no foundry has yet endorsed Merlin for signoff. Willis said that FTL is working with several foundries to reach that status.

Willis said FTL Systems probably has another few months to go on Merlin's early-release program and expects to have a production-ready version of the suite ready by the end of the year. Pricing will range from $10,000 to $50,000. FTL Systems expects that logic technology in the form of DLLs will be available from third parties.

- Richard Goering

EE Times

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