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PMC-Sierra multiprocessor with two E11K CPU cores

Posted: 06 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:pmc-sierra? multiprocessor? soc platform design methodology? rm11200? e11k?

PMC-Sierra Inc. introduced its third generation highly integrated 64bit MIPS-Powered multiprocessor at the Fall Processor Forum.

Using both the company's SoC platform design methodology and 90nm CMOS process technology, the RM11200 multiprocessor integrates two newly designed 1.8GHz E11K CPU cores with multiple high-speed memory and I/O interfaces, including dual DDR2, dual PCI Express, quad Gigabit Ethernet ports and HyperTransport.

"System designers face multiple challenges when developing high performance equipment, which include balancing the need for high I/O bandwidth, low memory latency, high processing performance and low power," said Steve Perna, VP and GM for the Microprocessor Products Division at PMC-Sierra. "The RM11200 uniquely addresses these critical challenges to provide our customers with optimal system performance and low power."

Addressing the high bandwidth requirements for next generation networking, storage and communications equipment, the RM11200 has dual 64bit DDR2 memory controllers that support frequencies up to DDR2-800 and 8bit ECC. The PCI Express interfaces support either dual 4-lane interfaces or a single 8-lane interface, and the quad Ethernet interfaces support automatic assignment into 8 queues per port and perform HW checksum assist. Additionally, the HyperTransport interface runs up to 600MHz link frequency, providing up to 10Gbps of full duplex bandwidth. All of the I/O interfaces support Direct Deposit, which allows external peripherals to write directly into the L2 cache.

The E11K cores

Building on the performance of the E9K CPU, each E11K core quadruples the Icache to 64KB, doubles the Dcache to 32KB, and delivers a total of 1MB of on-chip L2 cache, with ECC in both the L1 and L2 for data reliability. The dual 7-stage, symmetric superscalar E11K cores support full hardware processor-to-processor cache coherency using the 5-state MOESI cache coherency protocol, as well as full hardware I/O coherency over each of the I/O interfaces.

The XBAR connects the processor cores, memory and I/O interfaces together, and can support an aggregate bandwidth of over 1Tbps, with a 3ns port-to-port latency. The XBAR also uses a clockless technology, which cuts power by eliminating the need for a global clock. As a result, power consumption in the XBAR is proportional to the amount of data the XBAR is switching.

Designed for high performance networking, storage and communications applications such as enterprise routers, storage systems and DSLAMs, the RM11200 will be available in an 1152-pin Flip Chip BGA package. Initial samples of the device will start in Q2, 2005, with volume pricing estimated at $450. A comprehensive support product package, including datasheets, application notes, reference design and software, is available.





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