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Cadence, Artisan to optimize low-power chip design

Posted: 11 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? artisan components? library views? digital ic design platform? sage-x?

Cadence Design Systems Inc. and Artisan Components have collaborated to provide library views that enable designers to effectively optimize low-power chip designs. The companies will create and qualify Artisan library views based on the Cadence effective current source model (ECSM) format. These views are expected to provide customers with accurate delay prediction across a wide range of voltage levels and operating conditions using the Cadence Encounter digital IC design platform.

Customers are adopting methodologies that vary the supply voltage to enable a more effective trade-off between performance and power to meet the increased challenges of lower-power designs. These methods require additional timing views to predict chip performance at different voltage levels. The different voltage levels may be intentional variations for power savings or the result of IR drop and ground bounce.

Artisan and Cadence performed qualifications using Artisan's SAGE-X standard cell library and measured delays against SPICE while varying voltage, slew and load to achieve and verify the necessary accuracy levels for the ECSM (lib_ecsm) delay models at different voltage levels. The average difference in measured delays between SPICE and ECSM was 0.5 percent.

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