Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Controls/MCUs

Multicore MPUs go mainstream

Posted: 18 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:intel? multicore processor?

Intel Corp.'s decision to take the hydra-headed designs known as multicore processors into the volume realm starting next year raises a host of unanswered questions.

Intel president Paul Otellini declared that the company is about to drive microprocessors with more than one core into the computing mainstream, where they will face the scrutiny of both Wall Street and Main Street. On the other side of this Rubicon, a whole new set of techno-business battles awaits as engineers, computer makers and consumers sort through the new possibilities that multicore computing represents.

Designers must decide on core and cache architectures to maximize performance while keeping die size, power and yields from getting out of hand. Marketers have to figure out some new benchmark that might speak of both multiple cores and the thornier topic of multiple threads.

Computer makers see opportunities in simpler board layouts and threats in potentially greater commoditization in their already notoriously penny-pinching business. And OEMs and end users ask what is currently seen as the most troublesome question of all: What will the software cost?

The multicore designs could run multiple instances of an operating system or application. Some of these systems ultimately will be paired with so-called virtualization capabilities that create securely walled-off virtual machines for different tasks such as running Windows in one area, Linux in another and an instant-on DVD in yet another.

That promises cool new features for business users and consumersunless Microsoft, Oracle and other software vendors start demanding payment per core or per virtual machine, instead of per system.

"How do you bill? It's a really complex problem that Intel, IBM, Microsoft, Oracle and a lot of other people will have to come to an agreement on," said Michael Krause, a senior technologist in Hewlett-Packard Co.'s server group. "There are people in HP starting to work on this now. It's one of the biggest problems with multicore out there, and the industry has yet to figure it out."

"There's a huge war brewing between the hardware and software people on this issue," said Kevin Krewell, editor in chief of the Microprocessor Report. "It will probably go on for most of the next year."

Multicore processors are no strangers in embedded systems like Cisco's recently launched CRS-1 carrier-class router, which sports a 192-core Tensilica CPU. They also have staked out territory on the high-performance fringe of back-room servers. Indeed, Intel and Advanced Micro Devices are still trailing IBM and Sun Microsystems in the race to deliver a multicore server CPU.

Now Intel plans to take these designs into volume markets.

"This is a sea change in computing . . . a fundamental shift in how we look at the technology," said Otellini in his keynote at the Intel Developer Forum here last week. "In 2005 we will ship dual-core processors in every one of our market segments," using at least two different architectures, he added.

'Intel was blindsided'

Otellini predicted that by the end of 2006, 40 percent of Intel's desktop, 70 percent of its notebook and 85 percent of its server CPUs will be multicore devices. All future Intel CPU designs will be multicore. Intel Capital is getting into the act by funding startups that will accelerate the shift to multithreaded software, he added.

Intel's motive is clear. The 20-year-old trick of driving performance by turning the frequency crank hit a wall with Tejas-class Pentium chips that sucked and leaked too much power and gave off too much heat. Intel canceled the Tejas design earlier this year.

"Intel was definitely blindsided by the thermal issues around clock speed and leakage," said Martin Reynolds, a senior analyst with Dataquest.

Rival Advanced Micro Devices Inc. is breathing down Intel's neck on the multicore shift. Its engineers foresaw the multicore trend in the Hammer design, building arbitration logic into the part. Analysts expect dual-core Opteron and Athlon parts from AMD will hit in the second half of 2005, about the same time the first dual-core Pentiums and Xeons arriveall initially built in 90nm CMOS.

Analysts say AMD's latest single-core parts are yielding higher frequencies per watt than Intel's on similar design rules. "I conclude from that, AMD has more thermal headroom to scale chip frequency and stay within a typical 90W desktop processor," said Nathan Brookwood, market watcher with Insight64.

CMOS king Intel is likely to parry the early AMD advantage when it rolls out its first 65nm processors, something Otellini promised for late 2005.

Architecture is a thornier problem, a fact that is probably leading Intel to initially adopt at least two potentially competing approaches. One architecture will tap the relatively efficient Mips/watt notebook cores from its Centrino design team in Israel. But those cores do not yet support some of the current CPU features that certain servers and workstations require, such as 64-bit addressing.

Hence Intel's second line, based on existing desktop or server cores. This architecture will sport more features, but eat more power.

According to some reports, Intel has been so rushed to make the multicore shift that one of its first dual-core server chips will not even sport arbitration logic. Instead it simply slaps two cores on one die, asking the existing bus-contention protocol to sort out the doubled workload.

Cache considerations

Crafting the right cache architecture will also take time. Shared caches have the lowest latency, but are hardest to design. Intel opted to pack a whopping 26MB of cache on its Montecito chip, a member of the VLIW-based Itanium server CPU family that ships next year. Such huge amounts are not expected on the desktop or notebook chips that don't support multiprocessing, but Intel did say its first dual-core desktop CPUs will step beyond today's 2-Mbyte on-chip caches.

Once there are multiple CPUs on the die, workstation developers outside the Windows arena have an advantage over Intel. Because of the optimization of the local-bus protocol between processors, the sizes and configurations of the on-chip caches are highly software-dependent. It is possible to optimize a multiprocessing chip architecture for one relatively stable operating system and one small set of critical applications. It is almost pointless to optimize an architecture for a future operating system and a range of applications with differing localities of reference and I/O characteristics.

It is almost a given that each CPU on a multicore die will have its own Level 1 cache or caches. But will there be separate instruction and data caches, or a unified cache? How big will they be? Will a given cache be direct-mapped or multiway set-associative?

That's just a beginning. There are also questions about the interconnect scheme for shared or multiple L2 caches. Sun Microsystems Inc., in its Niagara chip, provided private L1 caches for each CPU core, but a shared L2. "That decision was based on a lot of modeling with our applications base," said Fred DeSantis, vice president for horizontal systems at Sun.

The protocol on the bus is another major issue. Under some circumstancesan embedded system with a fixed software load, for examplea simple arbitration protocol with no hardware to ensure cache coherency is sufficient, and in fact improves performance. In cases where the software load is more variable or unpredictable, a dynamically adjustable priority scheme may be necessary for bus arbitration, and a MESI or coherency protocol may be necessary.

Pentium-class CPU cores are already huge and power-hungry. And caches are notoriously hard to design for low power at high performance. Once Intel commits to placing a certain number of CPU cores on a die, designers may be forced to give up critical parameters in other areas, such as local-interconnect bandwidth or cache size, at the expense of overall system performance on some applications.

Marketers may have to do some fancy dancing, too. The first multicore products are likely to run at the same or slower clock rates as previous-generation parts.

In addition, nontechnical buyers may expect dual-core CPUs will sport twice the performance, which is theoretically possible. But Bill Siu, general manager of Intel's desktop group, said mileage will vary greatly depending on the number of apps running and their use of multithreading. Real performance gains may run a gamut from zilch to 70 percent, and on average probably will be somewhere around 25 percent, he suggested.

"It's difficult to quote a specific performance number," Siu said.

Wall Streeters spent much of last week trying to figure out whether the multicore chips will require bigger leaps in die size than previous X86 iterations. An extra few square millimeters in a Pentium or Xeon would immediately translate into lower profit margins for the world's largest chip maker.

Given few details by Intel, analysts speculated that the first 90nm parts would probably grow more than the typical next-gen Intel part, but that the size issue would quickly fall back in historical line with the advent of the 65nm process.

Soft issues

Meanwhile, the move to virtual machines on multicore architectures opens up new business models where many players can have access to more robust and secure spaces on a host of systems from servers to cell phones, said Reynolds of Dataquest.

"This has deep implications for all processors, and it's enough to drive people to buy new products," Reynolds said.

Intel is already designing into its CPUs the capability to virtualize hardware resources. Microsoft will enable the features in Longhorn, its version of Windows due in 2006.

Software vendors face technical as well as business issues with multicore. Current software only delivers performance benefits on processors sporting two to four cores with two threads each, according to Balaram Sinharoy, who designed IBM's multicore, multithreaded Power5 server CPU.

"The OS's schedulers have to get more sophisticated and over time I think they will," said Krewell of the Microprocessor Report.

As the software improves it will open the door to packing more cores supporting more threads on each die.

For OEMs, the move to multicore promises board-level savings in cost, power and size, but not without raising other issues. "Everyone is driving toward the single-socket mainstream server now, but we also worry this could commoditize a space where the typical dual-processor X86 server already sells for $1,500," said HP's Krause. "How will people differentiate their products?"

Whatever the problems and opportunities, multicore microprocessors are here to stay. "This is not a one-generation thing," said Intel's Siu. "The performance per watt on multithreaded and multicore processors is much more power and energy efficient than single-core designs.

"The multicore strategy is a long-term strategy. We are making a commitment all across the company to this," he added.

Rick Merritt

EE Times

- Additional reporting by Ron Wilson

Article Comments - Multicore MPUs go mainstream
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top