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IMEC claims silicide gate could enable 45nm process

Posted: 20 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:imec? 45nm? cmos processes? fully-silicided nisi?

IMEC has demonstrated the integration of fully-silicided NiSi gates on top of high-k gate stacks, claiming a potential breakthrough that would enable development of a 45nm manufacturing process.

The work is complementary to high-k gate stacks as replacements for silicon dioxide. However, because of poly depletion effects, it is widely held that polysilicon gates, which have become standard with current CMOS processes, are a roadblock to CMOS devices at and below 45nm.

The alternative is metal gate material. But the necessity to use different metal materials for p- and nmos transistors and accompanying barrier layers, to balance threshold voltages, present complexity problems.

Stefan Kubicek, senior device engineer at IMEC, here, said that easiest method of metal gate implementation is full silicidation of polysilicon gates, otherwise known as FUSI, in a scheme that results in a nickel-silicide gate. It can also be thought of as an extension of the polysilicon gate, since this is the starting material.

In addition FUSI can be used for both the p- and nmos transistor with a symmetrical threshold voltage in the region of 0.5V.

"It's impossible to meet the roadmap with polysilicon but FUSI shows readily the solution," said Kubicek.

IMEC has built nickel-FUSI gates over SiON and hafnium-based high-k gate stacks, to investigate the reliability of the gate stacks. FUSI does have some problems with variation in threshold voltage for, as yet, not fully understood reasons. "In the long term, full metal gates will be needed, especially for high performance," said Marc Heyns, an IMEC fellow.

Intel Corp. claims to have developed a high-k gate stack, but has declined to identify the materials. Intel's high-k gate insulator is thought to be hafnium-based, something it would be using in common with most other research groups. It is not known whether Intel is using a dual metal gate or a FUSI scheme.

Ongoing work at IMEC is targeting an integration scheme for FUSI that avoids CMP, IMEC said.

- Peter Clarke

Silicon Strategies

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