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Forte upgrades timing diagram tool

Posted: 21 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:chronology? forte design systems? timingdesigner v7.0? timingdesigner?

Claiming enhanced project management and timing interface design features, the Chronology division of Forte Design Systems has released version 7.0 of its TimingDesigner interactive timing analysis and diagramming product.

TimingDesigner v7.0's new project manager simplifies the exchange of timing information and allows users to more effectively manage the specification and analysis of high performance interfaces for their digital IC and board designs, the company said.

The tool now allows users to arrange multiple diagram components within one project. Components and blocks are arranged and displayed in a single tree, with a summary list of all constraint violations in the project diagrams.

Designers can also merge two diagrams from different components to create an interface that automatically accounts for component connectivity and helps manage signal duplication and propagation delays.

Designers can now also localize library management for specific diagrams and their associated paths, avoiding time-consuming network access to large library repositories.

To simplify analysis and save debug time, designers can now designate the use of only minimum or maximum values for their diagrams (as opposed to both minimum and maximum values) to perform best-case and worst-case timing analysis.

Other enhancements include waveform dividers to visually group signals together; font modifiers to better support documentation style guides; display of decoded values on valid edges of signals, derived signals and buses; and new built-in spreadsheet functions for improved analysis reporting.

TimingDesigner is supported on the Microsoft Windows, Sun Solaris, HP-UX and Linux platforms. TimingDesigner 7.0 starts at $2,640 depending on the configuration.

- Mike Santarini

EE Times





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