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Xilinx smooths EasyPath to take on structured ASICs

Posted: 21 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:asics? fpga? xilinx? easypath?

Xilinx Inc. is taking another whack at competing structured-ASIC vendors with a revised EasyPath program that it says boosts yields and lowers the cost of finished FPGAs.

Xilinx proposed EasyPath more than a year ago as its answer to ASIC vendors' efforts to lower chip costs by offering structured ASICs devices with prediffused intellectual property blocks that can be programmed using only a few metal masks. Even FPGA vendor Altera Corp. now offers mask-programmable devices that are functionally equivalent to its bread-and-butter FPGAs.

Xilinx tried a mask-programmable solution in the past but found the conversion process messy and expensive. When structured ASICs appeared several years ago, Xilinx decided to offer a way to let customers test only the parts of an FPGA being used in an actual design. Thus even chips that contained faults could be used, as long as the faults didn't affect the areas used.

But Xilinx couldn't guarantee that the chips would work properly if the customer decided to make changes after test. So while customers experimented with EasyPath, none got to the point where it was ready to lock down a design and move to volume.

Xilinx says it has fixed that problem. After FPGAs have been tested according to the EasyPath methodology, engineers can make changes to the I/Os and lookup tables, though the routing must remain fixed.

Xilinx also has expanded its test capability so that it can test for two bit streams per device. The second bit stream might be used, for example, to configure the FPGA to perform system diagnostics.

Xilinx claims EasyPath will beat any structured ASIC on most counts. The company says it can offer per-unit prices that are 30 to 80 percent below the normal cost of its FPGAs, and it promises to offer unit prices that are less than half those of competing structured ASICs by the second half of 2005. The nonrecurring engineering cost is a flat $75,000. (Devices tested for two bit streams will be nominally higher.) And because the end result is still an FPGA, customers don't have to convert to a new chip format and re-qualify their systems.

Xilinx is so confident EasyPath will cause jaws to drop that it has expanded the program to include its latest Virtex 4 and Spartan 3 devices, bringing the total number of devices covered to 28.

- Anthony Cataldo

EE Times

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