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Cadence, Magma establish timing model standard

Posted: 22 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:magma design automation? ic implementation system? effective current source model? cadence design systems? rtl-to-gdsii system?

Magma Design Automation Inc. has disclosed that its IC implementation system supports the effective current source model (ECSM) from Cadence Design Systems Inc. Already used by the Cadence SoC Encounter global physical synthesis RTL-to-GDSII system, ECSM is now the timing model of choice for Magma's Blast Fusion.

"As part of our efforts to provide Magma customers with more advanced timing analysis, Blast Fusion now supports ECSM as our delay modeling of choice for timing signoff," said Premal Buch, general manager of Magma's analysis and signoff business unit. "Achieving signoff-quality results in an RTL-to-GDSII flow depends on high-quality models, and nanometer signoff success hinges on the availability and use of accurate delay data, which ECSM provides using an extension to the current de-facto industry-standard format."

The industry's traditional library model, which represents delay as either a 2-D table or a polynomial equation, does not provide the level of accuracy demanded at nanometer geometries. This model begins to break down at 130nm and is especially problematic at 90nm and 65nm. An advanced timing model offering accurate and practical modeling of nanometer delay is mandatory, particularly for today's low-power applications which require a more effective trade-off between performance and power.

"Recognizing the accuracy and ease of modeling advantage of ECSM over the current traditional solution, we've made a conscious decision to open it up for use by the industry at large," said Wei-Jin Dai, vice president, encounter platform at Cadence. "We are pleased by Magma's decision to leverage ECSM in their product solutions and expect the rest of the industry to follow suit. ECSM provides accurate timing models for higher quality designs, improved QoS, and faster time-to-market with first-pass silicon."





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