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Cadence releases next-gen HW-based verification system

Posted: 25 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? palladium ii?

To help systems designers facilitate verification of complex SoC designs in the wireless, networking, computing and multimedia market segments, Cadence Design Systems Inc. released its Palladium II system, an integral part of its Incisive functional verification platform. Paladium II is a proven processor-based technology which the company asserts to be the most productive verification environment and an ideal investment for hardware and software co-verification and system validation.

Only one-third the size of the first-generation Palladium system, Palladium II, compared to its predecessor, has doubled its run-time performance at up to 1.5MHz and its industry-pioneering capacity of 256Mgates. It also allows usage of up to 61,440 I/Os, seven times that of the first Palladium system.

By aiding companies get to first software and silicon with greater speed and efficiency, the Palladium II accelerator/emulator optimizes the system design chain. This enables teams to develop and fully verify embedded systems software before receiving first silicon which cuts a chunk of the development time. Verification before silicon tape-out also allows finding bugs and optimally fix it in silicon as opposed to patching the software later.

"In general, processor-based technology supports higher capacity; the performance is much more predictable," said Ran Avinun, director of marketing for the acceleration and emulation division at Cadence. Processor-based technology such as Palladium II is more reliable in terms of compile time and capacity compared to FPGA-based technology. Processor-based technology also scales to support large designs, has the highest interconnect bandwidth and rides the silicon performance curve.

Avinun shared that customers have several requirements in acceleration emulation such as handling the design faster and facilitating a rapid design turnaround. "With the old FPGA-based system, it takes one to three days to compile. With this kind [processor-based] of system, the compile time is approaching 10 to 30Mgates an hour, which means that for the majority of the designs in the market, you can compile them in less than an hour. This increases productivity," he explained.

"Geometry drives the density that is why we shrunk the size of the system. Density drives the cost as well as the performance," stated Avinun. Palladium II is built in advanced 90nm silicon which leverages high-speed on-chip memory and multichip module (MCM) packaging technology. This also enables direct communication between every processor in the Palladium II system, enabling fast communication to run at 190MHz. For the Palladium II system, there are 768 processors per ASIC, two ASIC die per MCM, with a total memory of 128MB.

The new accelerator/emulator also has a multi-user mode which permits up to 32 users to independently run in-circuit emulation and simulation acceleration. According to Avinun, design engineers who would like to verify their own blocks or models very early in the design cycle can do it in parallel, and since models are relatively small, the system can be shared to many users. This is especially beneficial to multinational companies with R&D centers based in various locations such as China, Japan, Europe and the U.S., he added.

Early thumbs-up

"The reactions of those early adopters were very good; IBM and Nvidia are very satisfied with the system. We were able to deliver what we promised them," Avinun disclosed.

The first Palladium II installation was at IBM in Germany as they used the system to verify their newest servers. IBM utilizes Palladium II as a 256Mgate-emulation system running 24/7 with multi-user, worldwide access. The operation of Palladium II has verified over a million lines of firmware pre-silicon and has accelerated the system validation phase.

Meanwhile, more than 400Mgates of Palladium II capacity are deployed on multiple projects at Nvidia according to Brian Kelleher, VP of hardware engineering at Nvidia. He said that they will continue to choose the Palladium family particularly the new system because of proven performance advantages that the technology has provided them in the past.

"We are committed to continuing to work with Cadence as the new system provides even faster speed and efficiency, and we anticipate our verification productivity to significantly increase in the coming months. We look to products like the Palladium II system to help enable us to bring new products to the market on time, critical for success in the multimedia chip arena," Kelleher said.

Avinun said that their major competitive advantages compared to their competitors include compile time, run-time performance, capacity and multi-user capability. "What we expect is that customers will begin to utilize Palladium II initially for designs that require larger capacity and higher in-circuit simulation performance. For smaller designs and cost-sensitive applications, we expect customers to continue to use Palladium for a while and later switch to Palladium II," he added.

Verification environment

The advanced verification environment in the new system enables a comprehensive support for hardware and software co-verification. A capability included is support for the rich verification IP such as the Incisive SpeedBridge which connects devices of different speed and ensures that these devices will be able to communicate. Other features include availability of verification IP, integration with software debuggers, assertion-based acceleration, and support for Linux platforms and other design languages and standards.

The system also utilizes the Incisive transaction-based acceleration (TBA) which can deliver 100 times of the performance gain and up to 100s of KHz in streaming mode. According to Avinun, transaction-based verification is popular in the market because it allows design verification not only in signal levels but also in protocol levels as well. TBA supports SystemC/SCV, C++, un-timed/timed testbenches, as well as configurability of transactors. The modeling guidelines also allow customers and third party companies to develop their own transactors.

"The technology and performance of our Palladium II system extends Cadence's leadership position in the acceleration/emulation arena," said Christopher Tice, SVP and GM, Verification Acceleration, Cadence. "Building on our first-generation Palladium solution, we have worked closely with our customers to develop a product that is flexible enough to use today and meet the capacity and speed requirements of tomorrow. The Palladium II system provides our customers with what we believe is the best return on investment in emulation/acceleration."

- Reden Mateo

Electronic Engineering Times - Asia





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