ITC keynoters say designers need IC yield data

Chip yields are increasingly being determined as much by unseen design weaknesses as by process issues, experts at the International Test Conference here said Tuesday (Oct. 26).

In a keynote address, Bernd Koenemann, chief scientist at Mentor Graphics San Jose, California, facility, said design shortfalls are having a greater impact on IC yields. "It's the 'what-you-see-is-NOT-what-you-get' era", said Koenemann, "It's giving a lot of people sleepless nights."

In sub-wavelength processing, where feature sizes are larger than the wavelength that etches the feature lithographically, defects are increasingly design-related, according to Knoenemann. "These invisible defects, which cannot be picked up in traditional test flows, can create catastrophic effects," he said.

The situation affects transistor performance, matching and extraction and is a determinant source of device variability. It also complicates performance. Designs have meanwhile become context-dependent, meaning there are wide temperature variations inside chips. Over time, they can cause drastic power changes.

"We have observed variances from 40 to 110 degrees [centigrade] inside chips over time as they perform at low frequency and then at high frequencies," said Koenemann.

The result "is that it is becoming increasingly difficult for EDA tools to accurately design on circuit performance," Koenemann added. He called for test solutions that make test faults easier to diagnose and finding ways to feed back statistical information about potential yields into the design cycle.

Koenemann previously was a fellow at Cadence Design Systems, and was part of the IBM testing team acquired by Cadence.

Echoing Koenemann, another keynoter urged designers to test for systematic defects.

The emerging design-for-manufacturing model has been operating in three kinds of yield environments: random, parametric and systematic defects. "Systematic defects dominate today over the random and parametric defects", said Bob Madge, advanced product engineering at LSI Logic Corp. "Design needs yield information back into the design flow," said Madge. "The business model for producing today's chips demands that."

According to Madge, a theoretical ASIC capable of generating revenues of up to $500 million includes fixed costs such as nonrecurring engineering costs. The expected profit would be $220 million. However, yield-related testing could raise bad-yield costs, turning the profit into a $10 million expense.

Madge said that by providing constant feedback on the statistical yield data back into the design flow, profits could instead reach $190 million. "Your mileage may vary," he quipped.

LSI Logic has implemented a statistical post-processing methodology that Madge said partially answers the question of how a separate data flow of information about yields and a silicon flow can be merged to provide yield data back in design.

Mentor Graphics' Koenemann agreed: "We need to add yield data and defect learning into our methodologies to [provide fewer] sleepless nights."

- Nicolas Mokhoff

EE Times