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Partnerships key to EDA success in Asia

Posted: 01 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:gartner? eda? china? taiwan? yield?

In the last few years, we saw major players in the EDA industry increase their presence in Asia particularly Taiwan and mainland China. EDA players have been trying to help customers in the region reduce their time-to-market through better design tools. But where does the industry go from here now that yield is becoming more important? Do EDA companies just sit back, wait and see?

More and more electronic products are being designed and built using leading-edge technologies, which will require better design tools. According to Mentor Graphics CEO Walden Rhines, advanced designs featuring more functionality and lower geometries will demand advanced design tools. The challenge will be on designing for lower geometries.

Survey says

In its latest report, Gartner Dataquest said that the worldwide EDA software and software maintenance market will experience growth this year with revenues reaching $4.2 billion at a CAGR of 12.5 percent through 2008.

In a recent survey conducted by Gartner and EE TimesAsia, chip design activity in Taiwan is focused on consumer electronics, design services and automotive electronics. In the mainland, IC design is focused on communications and industrial electronics.

One important thing to point out in the survey is that designs for lower process geometries continue to increase in both Taiwan and China. The number of ICs designed for 0.35?m and higher geometries in China dropped by more than 50 percent while chips designed for 0.18?m and below increased by 9 percent.

Recently, one of the most important goals in the electronics manufacturing industry was reducing time-to-market. EDA companies had a field day coming up with new tools for new design issues. But time-to-market at the expense of yield is rapidly becoming a death trap as customers watch their bottom lines shrink. Staying on the break-even point is becoming hard and staying in business is starting to look even harder.

Major EDA players are now getting their hands dirty by delving into the actual manufacturing processes, putting emphasis on design for manufacturability. This is also partly being attributed to the increasing acceptance of 130nm and 90nm process technologies. Next-generation chips based on these lower-geometry processes require different materials such as copper interconnects. This in turn will require changes in the current set of EDA tools.

Chip companies aim to have a stable yield and keep the variance as low as possible. But where does this really start? Saying that it must start at the register-transfer-level is one thing. Having a tool that actually helps design engineers reduce the number of manufacturable structures is another.

EDA companies in the region have been forming partnerships with local firms. This allows them to increase their presence more rapidly. Vendors are also forming partnerships with local universities, training young EEs on a diet of specific design tools.

While industry players are trying to come up with more advanced design tools for customers, one thing is for certainpartnerships will have to be formed and nurtured, and EDA companies will have to be more involved in the actual design process to provide better tools. Vendors and customers are now putting their heads together to make design for manufacturability a reality.

- Dave Ledesma

Electronic Engineering TimesAsia





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