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Standard interface eases partitioning

Posted: 01 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:wlan? man? rf? mac? analog?

The concept of partitioning analog and digital portions of a wireless system with a standard interface is gaining ground in today's applications and will become a necessity for tomorrow's communications systems. The JESD96 serial link standard released in May 2004 by the Jedec JC-61 committee enables such RF-to-bits partitioning for WLAN and MAN systems.

Several factors are driving the need for a standard analog/digital interface. While some applications will drive toward being complete systems on a single chip, many practical implementations will find the optimum point to be a system on a few chips. That is partly because with each process technology shrink analog circuits are more difficult to optimize than digital circuits. So rather than drive all components into a single system chip, many engineers are calling for a smart partitioning of analog and digital functions in wireless systems.

This new partitioning allows the radio chip to be more complete, opens doors to multivendor implementations and allows the modem and media-access control (MAC) functions to be embedded with other communications processors, perhaps even in the host. A well-partitioned system with serial digital I/O goes a long way toward reducing the total system cost, improving performance and reducing development risk.

Such RF-to-bits partitioning may also have practical benefits when it comes to getting regulatory certification for wireless systems. Current Federal Communications Commission (FCC) rules require a module to be certified as one physical entity. Thus, for applications that require the radio to be physically separated from the modem, any changes to the motherboard require recertification.

But the FCC is considering new rules that relax those constraints if the interface between the RF and the digital modem is digital and the components are certified together as a matched pair. In that scenario, recertification is not required for changes made to higher networking layers and system software that do not affect the transmit characteristics of the radio.

For these technical and regulatory reasons, the smart-partitioning philosophy is gaining momentum in the industry. Multiple-industry consortia are working on application-specific RF-to-bits interface standards within the cellular and broadband wireless industry.

The JESD96 is a point-to-point serial protocol optimized for transfer of sampled digital data and control information between a front-end device such as an RF transceiver, and a back-end device such as a digital modem. The high-speed serial link offers high-data bandwidth with a minimum amount of data and control latency.

It uses a low-overhead protocol that can be implemented with a low gate count and low analog complexity. The flexible frame formats, clocking modes and other programmable modes allow multiple collaborating vendors to create a common interface among their devices.

The basic interface consists of three differential signals totaling six pins. A DDR clock signal is sourced by the RF transceiver on one pair of pins. Two additional pairs of pins provide synchronous non-return to zero data transfer from the RF transceiver to the digital modem and back.

The source-synchronous signaling eliminates the need for an embedded clock; hence, the requirement for a clock recovery PLL on the digital modem.

Electrical signaling is specified for four different power modes that are distinguished by different termination impedance levels offering a flexible trade-off for applications with smaller physical separations. The high-power mode uses a standard differential source and load termination impedance of 100 ohms. This mode enables data links with rates up to 2.3Gbps per data pair and a maximum distance of 50cm. Multiple data lanes can be used for increased bandwidths or slower clock speeds.

A simple protocol provides three concurrent logical channels for communication of streaming, control and register data. Bits in a header field within each frame select the use of these channels.

RF-to-bits target

The JESD96 offers three key features that make it ideal for the RF-to-bits application independent of wireless standards and schemes.

First, a robust low-voltage differential-signaling variant similar to HyperTransport helps reduce output-switching noise, a key requirement for sensitive RF and analog circuits. Differential signaling is less susceptible to common-mode noise than single-ended schemes, thus making it possible to use lower signal-voltage swings.

The differential signal cancels magnetic fields, so it also tends to radiate less noise. Low-swing signaling with a current-mode driver reduces switching noise and makes power consumption independent of clock and data frequency.

Second, a flexible clock frequency allows the radio to be the clock master and a functional slave. The choice of clock frequency is critical to the RF plan used by the RF device. The clock frequency can range from the low megahertz up to 1.15GHz as dictated by bandwidth and latency requirements and the frequency plan of the RF transceiver.

To minimize spurious emissions, the clock frequency must be selected so that the harmonics do not fall within the bands of interest. Also, a source-synchronous clocking scheme simplifies the digital modem, reducing the complexity introduced by the flexible clock speed option.

Third, the serial link helps to reduce the pin count on the radio chip. This not only reduces costs, but, more important, allows the radio device to be packaged in a low pin count, accurately modeled package. This will become more important with future multiple-input, multiple-output systems.

The ability of the radio to control the high-speed serial clock frequency and a simple protocol makes it suitable for integration on a radio device and differentiates it from existing protocol-intensive standards like PCI Express, RapidIO and Infiniband.

- Noman Rangwala

Marketing Manager, Broadband Wireless Products

Analog Devices Inc.

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