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ST MCU based on the SmartJ RISC architecture

Posted: 02 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:stmicroelectronics? st? mcu? smartj? risc architecture?

STMicroelectronics (ST) unveiled a new smartcard MCU in its ST22 range based on the SmartJ Java-accelerated RISC architecture, which integrates 256KB of EEPROM memory with a high performance CPU to support the demands of multimedia applications on the latest mobile phones.

"The ST22N256 is perfectly in line with the growing demand for secure high-performance chips with high-speed interfaces and a large memory capacity, for use in 2.5 and 3G SIMs," said Reza Kazerounian, the company's GM for its Smart Card ICs Division. "ST already offers the largest range of secure 32bit processors for smartcard systems, and will remain at the forefront of smartcard silicon suppliers as 3G takes off."

The SmartJ CPU core at the heart of ST22 Family, which the new ST22N256 now combines with 256KB of EEPROM, is a 32bit RISC-architecture core developed specifically to provide very fast execution of Java. The ST22 augments its own highly efficient native RISC instruction set with a hardware decoder that directly converts Java bytecodes into native microcode instructions, eliminating the overhead and lower performance of processors based on Java emulation. According to ST, the result is not only very fast Java execution but also reduced power consumption.

With the quantity and size of users' MMS messages increasing, the company said, operators will now be able to provide increased storage for subscriber data without impacting user friendliness, due to the exceptional performance of the ST22N256's SmartJ processor, and its communication through a fast Asynchronous Serial Interface (ASI) which enables 440kbps communication speeds with mobile equipment, in line with the fastest deployments of ISO 7816 in the GSM world. Two additional serial I/O ports are also provided.

The SmartJ CPU core

The Java-accelerated CPU, with 24bit linear memory addressing, is complemented by 368KB of on-chip ROM, 16KB of RAM, and a set of standard peripherals and custom plug-in circuits. Logical and physical security mechanisms are fully integrated into the silicon, including a hardware Memory Protection Unit for application firewalling and peripheral access control, and a protected Context Stack. The core includes dedicated DES (Data Encryption Standard) instructions for Secret Key cryptography, and a fast Multiply and Accumulate instruction for Public Key (RSA) and Elliptic Curve cryptography, plus a CRC (Cyclic Redundency Check) instruction. A firmware cryptographic subroutine library is located in a secure ROM area to save designers the need to code first-layer functions, added ST.

The ST22 product platform is supported by a comprehensive Integrated Development Environment, which allows coding, compilation and debugging using a common interface. It provides a code-generation chain that includes a C/C++ compiler, a native and JavaCard assembler and a linker, plus a SmartJ instruction set simulator, C/C++ source level debugger, and hardware emulation tools.

The press release states that the SmartJ development methodology allows customers to significantly reduce the time and cost of developing secure applications. It supports concurrent hardware and software development, multiple development teams and IP reuse, as well as security evaluation to the Common Criteria and the use of formal methods for security assurance through executable high-level specifications and model checking techniques.

Manufactured using 0.15?m technology, the ST22N256 is already available in sample form, with volume production scheduled next year. Product pricing is between $4 and $5, depending on quantity and final packaging.

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