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Infineon touts chip-card density increase

Posted: 05 Nov 2004 ?? ?Print Version ?Bookmark and Share

Infineon Technologies has developed a chip-card controller based on a face-to-face interconnection technology the company says can deliver a 100X improvement in memory over today's chip cards, while just doubling chip area.

The company demonstrated a 1MB version of the chip card security controller made using the 'chip sandwich' technique at the Cartes and IT Security exhibition in Paris that starts Tuesday (2nd Nov).

Infineon says the chip card ICs would enable new and novel applications for mobile phones and smart cards.

Samples of the chip card controller will be available next spring, with volume production, on a 0.13?m CMOS process scheduled to begin in the second half of 2005.

For design-in support, Infineon has released a complete set of development tools including a Software Development Kit and an emulator.

The first application of the 1MB security controller will be in SIM cards, where the demand for higher memory capacities is the greatest. Using the face-to-face interconnection technique and existing technologies like EEPROM or TWINFlash, Infineon says it can build an ISO-compliant chip card microcontroller offering up to 20MB of memory. This is expected to be available in the second half of 2006.

The initial 32bit chip card controller, dubbed the SLE88CFX1M00P, provides eight times the memory capacity of today's chip card controllers with 128Kb of memory. It combines the 88 family's integral security concept, its integrated intelligent power limitation system for very low power consumption and powerful peripherals.

"Existing robustness constraints of ISO specifications limit chip card ICs' area to a maximum of 25 square millimetres, with restrictions in functionality enhancements and price-competitiveness, as expensive process shrink technologies have to be deployed," said Juergen Kuttruff, VP and GM at Infineon's Security unit of the Secure Mobile Solutions business group.

Kuttruff says Infineon is the first to break this barrier by using chip interconnections and a 130nm process, providing cost-effective chip card ICs with sizeable extension of memory, while complying with ISO requirements on mechanical stress.

The advanced stacking method can be visualized as a sandwich in which the two buttered open-faced sides, meaning the chips' functional areas, are laid one on top of each other. Without extra-wirebonding, the chipsfor example a security microcontroller and a memory chipare mechanically and electrically interconnected via hundreds of tiny contact pads on top of the chips, resulting in higher performance and memory capacity on the same chip area, while at the same time fitting into a standard chip card specific package.

Depending on hardware customization or application needs, Infineon says such a flexible approach allows stacking of chips with diverse interfaces, such as USB, SPI (Serial Peripheral Interface) bus or ISO14443 interfaces, as well as ASICs and FPGAs, as well as and chips manufactured using different processes and technologies, such as EEPROM, Flash or NROM (Nitrided Read Only Memory).

- John Walko

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