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Verisity, TransEDA unite respective verification solutions

Posted: 09 Nov 2004 ?? ?Print Version ?Bookmark and Share

Verisity Ltd, a supplier of verification process automation (VPA) solutions, and TransEDA, a provider of ready-to-use verification solutions, have jointly announced the integration between vManager and VN-Cover.

VN-Cover is a comprehensive code and FSM coverage solution that identifies unverified portions of simulated HDL designs. One of the tool's strengths includes the ability to deliver vendor-neutral coverage across simulators, languages, and platforms. In addition, its "deglitch" and "coverability analysis" capabilities enable the industry's highest accuracy for coverage measurement. By integrating with Verisity's vManager, the industry's first project-level verification management system, the companies will now offer a project-wide solution for combining all sources of coverage from specification to closure.

The VN-Cover integration follows a recent integration of TransEDA's specification coverage tool, VN-Spec. VN-Spec fills a gap in front-end verification by tying original specification documents to both implementation and verification flows, using requirement traceability graphs to define specification coverage metrics.

The TransEDA VN-Cover integration enables Verilog, VHDL and mixed-language code coverage to be collected and used for project-level verification by a greater number of engineers. The new VN-Cover integration completes total coverage measurement with mixed-language code coverage, in addition to functional coverage provided by Verisity's Specman Elite and assertion coverage of PSL, OVL and Checkerware. Code coverage data in Verilog and/or VHDL is collected during simulation runs and imported to vManager for analysis, display, and reporting of the integrated total coverage model and project management.





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