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TI, Xilinx partner on FPGA-based deserializer reference design

Posted: 10 Nov 2004 ?? ?Print Version ?Bookmark and Share

Texas Instruments Inc. (TI) and Xilinx announced the availability of an FPGA-based deserializer reference design that they have jointly developed.

According to the two companies, the new reference design, which deserializes bit streams from TI's ADS527x ADC family, and accompanying application note provide a quick and easy solution for designers to integrate a serial, high-speed LVDS receiver into the Xilinx Virtex-II series, Virtex-II Pro and Spartan-3 FPGAs.

Systems designers can now effectively leverage the serial-to-parallel processing capabilities and software programmability of FPGAs to accelerate operations for specialized, high-performance processing functions, the press release stated. It further said that the ability to achieve much higher levels of overall system performance is especially important for multi-channel applications such as ultrasound, instrumentation and wireless communications.

The deserializer reference design accepts up to eight channels simultaneously and provides automatic de-skew and clock alignment functions. Each ADC output is serialized and transmitted through a separate LVDS serial pair, and an independent frame clock and serial data clock are provided to allow for easy de-serialization. The press release also said that the Xilinx reference design provides the necessary timing to accept these extremely fast input signals and translate them into commonly used parallel output buses.

The serial LVDS interface format provides several advantages to the system manufacturer. Lower pin count, both on the ADC and the FPGA, means less routing lines and lower cost boards, the two companies explained. The LVDS interface itself is a differential current mode interface that provides both immunity to external noise and extremely low crosstalk injection of noise into the PCB, they said. These advantages translate to lower cost and higher system reliability.

The ADS527x family of eight-channel ADCs includes 40-, 50-, 65- and 70MSPS versions in 12bit resolution, and 40-, 50- and 65MSPS versions in 10bit resolution. All products in this family are pin-compatible, providing a simple upgrade path in both sample rate and resolution. In addition, the ADS527x family features a signal-to-noise ratio of 70.5dB (60.5dB for the 10bit family) at 10MHz input frequency and 123mW of power per channel at 65MSPS (138mW/channel at 70MSPS) - said to be the lowest power of any competitive product.

Designers can obtain more detailed information on how best to interface Xilinx FPGAs to TI's high-speed data converters for their specific applications by going to TI's website. The LVDS reference design files can also be downloaded directly from Xilinx's website.




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