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Faraday platform targets L4 to L7 switching

Posted: 16 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:packet processing? risc? platform asp? fpga? asic?

A lot of hardware has been thrown at wire-speed L2 and L3 packet processing. Cost-sensitive developers use RISC-based platform ASSPs and hope their buffers are deep enough to absorb the delays. The adventurous use network processor chips with elaborate supporting memory, and those truly in need of a speedy solution develop cell-based ASICs to devour packets on the fly.

But when packet classification extends to L4 and above, where there is little agreement about algorithms or performance targets, the game changes. Traditionally, this is a job for FPGAs: Common elements of the problem go into a small foundation ASIC (or are implemented in off-the-shelf chips), and a big FPGA handles wire-speed sorting. But the FPGA can add $1,000 to the BoM.

With the emergence of structured-ASIC technology, Faraday Technology Corp. saw another alternative: a platform ASIC with a large, embedded array of metal-configured logic. The initial implementation, the NetComposer I, combined an ARM4-compliant CPU core, a high-speed switching fabric and control-plane I/O modules with a large block of what the company calls metal-programmable cell arrays. High-speed, packet-tuned DMA and an unusual centralized data coherency engine increased data efficiency. Software on the ARM core handled transaction setup and teardown, with actual packet processing done in the configurable array.

The follow-on, NetComposer II, adds an eight-lane serdes block. As is becoming common, the Serdes core is configurable to support multiple protocols, including Gigabit Ethernet, Xaui, PCI Express, HyperTransport, RapidIO, SPI 4.2, Fiber Channel and serial ATA. Faraday rates the Serdes block at up to 5Gbps per lane.

What is not common about the Faraday Serdes blocks is their small footprint. "About a year ago, at the end of a fast analog Serdes design, we realized that in 130nm and below [processes], the typical mixed-signal approach to Serdes design was not going to be economical," said Charlie Cheng, vice president of the international business unit at Faraday. "The analog components are large, with a lot of white space around them for noise isolation."

So Faraday devised an all-digital approach: oversample the incoming waveform, digitize and correct it, and then pass a digital signal on to the data separator circuitry. "We estimated that with UMC's 130nm process we should be able to run the digital front-end at 5GHz or 6GHz," Cheng said. Test silicon proved out the estimate.

The resulting Serdes fits its entire PLL into two pad slots. Faraday says a complete PCI Express lane will fit into 0.25mm? and occupy 12 pad slots, compared with as much as 0.85mm? for one competitive vendor and up to 22 pad slots for another. A HyperTransport-to-PCI Express bridge block supports the Serdes area.

The NC-II also contains an area of metal-configured logic that provides 1-3 million logic gates and 0.5-1.5Mb of SRAM for the implementation of packet inspection, encryption/decryption, specialized I/O controllers or whatever content processing the application requires.

Configurations can be turned around in weeks. Faraday estimates that the metal-configured array gives up 10 percent in peak speed and about a third in area efficiency compared with a full cell-based design, in exchange for the quick turnaround and the low NRE and unit costs.

A 62-pin, metal-configured I/O block on the NC-II, meanwhile, can be set up to handle standard-logic I/O, PCI or PCI-X, level shifters or other requirements.

The target unit price for a configured chip is less than $50 in quantity.

- Ron Wilson

EE Times

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