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Sonics tunes next-gen architecture for rich media

Posted: 16 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:ip? wireless? rich media? mx architecture? interconnect?

Sonics Inc. has seen its interconnect intellectual property (IP) used primarily in wireless applications and digital consumer devices where power consumption was not a serious issue. But now the company, with the introduction of its MX architecture, is aiming for the same handheld "rich-media" applications that just about every other IP vendor and chip house is targeting. That has required some adjustments.

Sonics is part of a small industry that has sprung up around a dilemma. As the number of blocks in typical soc designs increased, a funny thing happened to the idea of importing predesigned IP and simply stitching it together: The design work necessary to do the stitching became a substantial portion of the overall front-end workload.

At the same time, the interconnectnot just the placement and routing, but interconnect architecture as wellbecame increasingly critical to the final performance of the chip. When an SoC was a single embedded cpu core with internal caches, a dram controller and some simple peripherals, the interconnect was not an issue.

But consider a more challenging SoC scenario: a design with several processors. Drop in a large SRAM that has to DMA back and forth with the caches and main memory. Add high-speed data sources. Upgrade the DRAM interface to DDR2, with demanding bandwidth requirements. Now try to serve media data streams that must observe maximum allowable latency requirements.

Not only is the native bus for one of the CPU cores not the obvious solution, but it may not be obvious that there is a solution.

Such needs have led oncesimple CPU buses to evolve into complex multilayer interconnect schemes. The ARM AMBA architecture is a case in point. The problem has also supported a small group of companies, independent from any one CPU vendor, in the interconnect IP business. Sonics is among them.

Sonics argues that the role of interconnect IP is not just to establish a physical connection between blocks. Rather, it is to translate the SoC architect's data flow requirements into a fabric that can meet them.

This means physical interconnect, certainlyand embedded in the Sonics scheme is the Open Core Protocol definition, which the company has promoted through the eponymous industry organization. But the Sonics approach goes beyond just signal definitions and physical-layer protocol to wrap transactions between blocks in something like a link-layer protocol and to implement the whole thing with an application-specific interconnect fabric, generated from the system requirements. The fabric may be a shared-access bus, a dedicated-port crossbar or a combination of the two, as dictated by the bandwidth and latency requirements of particular connections.

The new MX architecture required some adjustments, starting with a thorough attack on energy inefficiencies. In part, this was achieved by simply keeping the clock rate low on the globally synchronous Sonics interconnect fabric and its interface: MX targets 100MHz to 200MHz designs. That means not only lower dynamic power but the ability to design in the low-leakage versions of common 130nm processes, further reducing energy consumption without the need for elaborate voltage-island, back-bias or cell-substitution schemes.

Ron Wilson

EE Times




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