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Truths, lies and FPGA prototypes

Posted: 16 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? prototype? asic? i/o? clock divider?

Rizzatti: Unquestionably, traditional FPGA prototyping tools need improvement, and the industry needs a standard metric to help evaluate those solutions.

Almost anyone can place two FPGA devices on a board and declare, "Ready to prototype." This is not exactly true with two FPGAs, and unrealistic with more than five or six.

A quick scan of a catalog of FPGA prototyping offerings will reveal an endless list of companies, often the size of a cottage industry. The question is what differentiates them? If you feel compelled, dig into the websites of a few of these FPGA prototyping vendors or pick up and browse one of their data sheets. Very quickly, you will be saying, "Here is another bucket of FPGAs with no software support."

The difficulty in differentiating one offering from another gets further compounded when you take a peek at capacity and performance specs. They will puzzle you at best or leave you dazed at worst.

First, the lack of an official standard to measure the capacity of an FPGA, or even implicit consensus on the metric, opens the door to manipulation. By way of ambiguity, a vendor may offer you a platform for 12Mgate designs. Close scrutiny will reveal the presence of two Virtex-II XC2V6000 FPGAs thatat mostwill map 1 million ASIC gates. The vendor neglected to mention that those 12Mgates were system gates. Ultimately, it becomes a semantic argument.

Gates aside, speed specifications will impress and confound you. But beware. Xilinx claims a top speed of 400MHz for the fastest version of the Virtex-II. By the time you map a 3 million ASIC-gate design onto five or six of the largest of them mounted on an FPGA prototyping platform, you may execute at a few MHz at best. Where did all those MHz go?

First, with propagation delays of a few ns per I/O pad, five interconnected FPGAs will take a bite out of the maximum speed of execution. Second, the limited I/O pin count of FPGAs will force you to apply multiple data rates on I/O signals that will cut speed by at least the same multiplying factor. Third, the presence of memories with multiport access will further tax the speed.

Realistically, you'll be lucky if you execute your design at 10MHz.

And, how about distributing those 3 million ASIC gates to those five FPGAs? FPGA prototyping vendors offer neither partitioning tools nor an automatic means to route the often complex clock trees with hundreds of gated clocks and clock dividers. In fact, they don't offer tools to manage multiple data rates on I/O boundaries.

And yet, once you have spent long days and weekends mapping those darn 3 million ASIC gates, you are ready to prototype. But are you really?

If you plan to validate embedded software, a jtag connection to a software debugger may be all that you need. If you plan to debug your hardware, you better look elsewhere. At best, those undifferentiated buckets of FPGAs sit on a signal-level interface and unveil their guts only via static probes subject to recompilation every time you change them. You may even fail to recompile if you run out of resources. Needless to say, design debugging gets nightmarish and makes your life miserable.

Unquestionably, traditional FPGA prototyping tools need improvement, and the industry needs a standard metric to help evaluate those solutions. Vendors should consider developing new architectures to offer more capacity and software testbench capabilities, along with a means of accelerating the verification process. An ability to validate embedded software is critical, which means that they should be flexible enough to support hardware designers and serve the embedded-software development community.

Until then, you need to consider the old axiom "caveat emptor."

- Lauro Rizzatti
General Manager
Emulation and Verification Engineering USA

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