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Magma, Aldec deliver front-to-back FPGA design flow

Posted: 18 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:magma design automation? fpga? aldec? active-hdl 6.3? palace?

Magma Design Automation Inc. and Aldec Inc. have completed the design flow interface between active-HDL 6.3 and PALACE version 2.4. The integration of the two products automates the data exchange of graphical design capture, mixed VHDL and Verilog verification and physical synthesis providing an efficient, easy-to-use solution for Actel, Altera and Xilinx designs.

According to the companies, they have implemented a new design flow option in Active-HDL to utilize the functionality of PALACE for physical synthesis of FPGA designs. When the design flow for the physical synthesis tool is enabled, a window displays the physical synthesis option button that allows the designer to control the process performed by PALACE. When combined with the FPGA vendor-supplied or industry-supplied FPGA synthesis tools, active-HDL and PALACE provide a fully integrated front-to-back tool flow that delivers higher quality results.

While PALACE focuses on optimization of the synthesized netlist and architecture-specific implementation, active-HDL provides a graphical design capture, mixed-HDL simulation and debugging environment. Once the design is verified in Active-HDL, the RTL is synthesized and optimized using PALACE through the automated design flow manager.

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