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Cadence Encounter Conformal 5.0 with enhanced verification capability

Posted: 18 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? encounter conformal technology? encounter conformal 5.0?

Cadence Design Systems Inc. announced enhancements to its Encounter Conformal technology. According to the company, Encounter Conformal 5.0 helps customers with enhanced verification capability to ensure that the tapeout accurately reflects design intent.

Important new capabilities in Conformal 5.0 include FPGA support, clock domain checking and advanced datapath verification, Cadence added.

Conformal technology now extends equivalency checking to FPGA prototypes through the Synplicity design flow to Xilinx devices, with support of Altera devices to follow. The product also addresses the rapid increase in the number and complexity of clock domains with formal verification of clock domain crossings. This release of Conformal features SystemVerilog support, complex datapath verification enhancements, and across-the-board equivalence checking capacity and performance improvements.

Conformal technology checks the functional equivalence of versions of a design at various critical stages to help the designer quickly identify and correct errors, the company explained. Conformal equivalence checker does not share technology with design tools, ensuring an independent verification audit of the design flow. Cadence said this complete, independent verification minimizes design re-spin risk.

"Conformal 5.0 substantiates the Cadence investment in the Conformal formal verification technology acquired with Verplex last year," shared Michael Chang, VP of R&D in Cadence's Formal Verification division. "We are constantly enhancing this technology to compress the verification cycle and meet the challenges of next-generation designs."

Conformal 5.0, now part of the Cadence Encounter digital IC design platform, is already shipping.

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