Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Memory/Storage
?
?
Memory/Storage??

TI, Ramtron tip 4Mb embedded FRAM technology

Posted: 23 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:texas instruments? ramtron international? fram? ferroelectric random access memory?

During the Non-Volatile Memory Technology Symposium 2004 (NVMTS2004) last week, Texas Instruments Inc. and Ramtron International Corp. presented more details of their efforts in the ferroelectric random access memory (FRAM) market.

In a paper presented at the Orlando, Fla.-based event, TI and Ramtron described a "functional" embedded FRAM (eFRAM) using a 130nm process technology. The five-level metal technology also features copper interconnects and fluoro-silicate glass (FSG) as the material of choice.

TI and Ramtron are said to be working together to develop a 4Mb FRAM. TI has been working on FRAM technology for several years, but the company says that its non-volatile memory program is on track. "We are still shooting for products in 2005," according to a spokesman for TI.

Initially, TI will manufacturer FRAMs on a foundry basis for Ramtron. The first parts are due out in early 2005, according to the TI spokesman. Then, TI is expected to produce standalone eFRAMs by end of 2005. The company is said to roll out 4Mb eFRAMs.

In the paper, TI and Ramtron claim that eFRAM has several advantages over embedded flash, DRAM and SRAM. The technology "offers the combination of fast-write times (

While FRAMs are promising, the technology has seen limited adoption due to scaling and manufacturing issues. Current FRAMs have been limited to smaller densities and 0.35?m technology.

Ramtron and Fujitsu Ltd. have introduced 1Mb FRAMs. At present, Fujitsu serves as a foundry for Ramtron. However, Samsung and others have struggled to ship FRAMs in the marketplace, according to analysts.

TI appears to have solved some of the manufacturing issues. TI's FRAM module consists of a ferroelectric capacitor (FCAP). The capacitor stack is composed of a titanium aluminum nitride (TiA1N) diffusion barrier, TiA1N hardmask, and an iridium bottom electrode processed via MOCVD technology, according to the paper.

It is also implemented with only a two-mask adder to standard CMOS. "The capacitor area is defined using the FCAP mask and etched using a multi-step reactive-ion etch process," according to the paper. "The second mask, VIA0, is used to define multi-level W vias, which create electrical connection from the first metal level to either the ferroelectric capacitor or the underlying contact."

- Mark LaPedus

Silicon Strategies





Article Comments - TI, Ramtron tip 4Mb embedded FRAM te...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top