Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Amplifiers/Converters

On-chip VCOs can be digitally tuned

Posted: 01 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:vco? cmos? analog? digital? lc?

Synchronous systems, whether analog or digital, all use a clock reference signal, typically generated using a high-frequency PLL, where power consumption, frequency range and accuracy, noise level and jitter are critical system-level parameters. In these PLLs, one of the most challenging blocks to design properly is the voltage-controlled oscillator (VCO).

One common approach to designing VCOs in CMOS is to build a ring oscillator using a cascaded set of inverters that feeds back into itself. Adjusting the delays of the inverters tunes the frequency of oscillation. While generally simple to design and having wide tuning ranges, ring oscillators unfortunately have performance limitations, such as excessive noise and jitter, that make them inadequate for high-performance applications such as wireless communications. For such applications, inductor/capacitor-based (LC) VCOs are a better choice.

However, designing high-speed LC oscillators in deep-submicron CMOS processes has major challenges. Limitations in the accuracy of transistor and wire models, as well as normal manufacturing process variations, can cause the performance of the realized design to diverge significantly from what the designer originally intended. For example, variations in layout parasitics can cause the center frequency, frequency range and performance of an LC oscillator to change significantly.

One approach to creating a robust design capable of tolerating such variations is to implement a digital autocalibration scheme using feedback. In the case described here, we used a digital autocalibration scheme consisting of an ADC, capacitive banks and a finite state machine to compensate for a wide range of process modeling errors and variations. This approach realized LC VCOs operating at 6GHz (typical) in 0.13 CMOS processes, with 1ps (rms) random jitter (typical).

Digital calibration

In our approach, a key goal was making the calibration process transparent to the end user. This meant incorporating the autocalibration scheme entirely within the PLL. A necessary trade-off was a significant increase in the PLL settling time (due to added calibration time), but that is a negligible penalty for many applications.

Conceptually, the circuit operates as follows: Since the VCO frequency is proportional to 1/square root of (L x C), tuning is done by connecting and disconnecting banks of capacitors within the VCO. Calibration inputs to the state machine are the lock signal, the (8bit digitized) VCO control voltage (Vctrl) and a thermal-compensated voltage reference. The state machine starts the calibration process at the power-on reset, and sets the VCO to the lowest frequency by setting the capacitance to maximum. The PLL then attempts to lock. When the PLL fails to lock, the state machine increments the VCO frequency. The calibration is run until PLL lock is finally achieved with the Vctrl at an optimal value.

This particular PLL design was intended to operate at three distinct frequencies (3.2-, 4- and 4.8GHz) and used more than 60 calibration steps. It featured a full-rate differential output clock and a half-rate quadrature output clock. Power supply was 1.35V (min). Random jitter was specified at 1ps rms and calibration time was 3.5ms (max).

As noted, LC oscillator specifications are defined mainly by the inductances and capacitances inherent within the design. Layout parasitics in 0.13?m CMOS can have a significant impact, particularly when defining the capacitive-bank values. To accurately extract the parasitics from the drawn layout and model their effects, the designers used Assura, a physical-verification tool that includes an accurate parasitic extractor fully integrated with the Cadence Virtuoso schematic-entry tool. This allowed direct cross-probing of parasitic elements between the schematic and layout.

Simulating the design posed a significant challenge for the design team. Transistor-level simulations of the PLL were extremely slow due to the circuit's complexity, the speed of the output clock and the requirement for high-accuracy simulation settings.

Simulation runtimes for the entire PLL loop after adding charge pump, VCO, phase-frequency detector (PFD) and dividers could exceed four days--an unacceptable figure given the large number of simulations the design team needed to run.

To reduce simulation runtimes, the team used behavioral models for current sources, dividers and PFD for all but a few of the top-level PLL simulations. Full transistor-level simulation was primarily limited to power supply-induced jitter analysis and for final checks like verifying electrical connectivity of current sources and biases.

Overall loop

To verify the performance of the overall loop, the team combined mathematical analysis, behavioral simulation and transistor-level simulation. Matlab calculations helped to verify stability of the loop over worst-case corners and to calculate conversion of thermal noise into output rms jitter. Mixed behavioral-transistor simulation with Spectre-Verilog confirmed basic loop functionality, such as frequencies, divider ratios and calibration settings. In these cases, simulation runtimes were shorter, averaging two to five hours each.

One of the most important specifications in the design was total output jitter. To estimate the PLL jitter, the designers had to account for both random (Gaussian) and power supply noise. Random noise from the charge pumps and VCO was simulated at the block level using Spectre RF, an option of the Virtuoso Spectre Circuit Simulator optimized for simulating RF transistors in the frequency domain. Matlab was then used to convert results to jitter in picoseconds (rms) measured at the PLL output. Designers similarly addressed power supply noise simulation by applying a noise stimulus to the power supply and measuring the resulting cycle-to-cycle jitter at the PLL output.

The final design ensured optimum operation of an LC VCO implemented in 0.13?m CMOS across a range of temperatures and process variations. By employing a sufficient number of steps in the architecture, we could also ensure the VCO operated correctly at different calibration settings. This added flexibility increased the design team's margin for success and helped ensure the PLL could be used in a wide variety of applications.

- Franck Banag

Lead Design Engineer, Analog/Mixed-Signal/RF Group

Cadence Design Systems Inc.

Article Comments - On-chip VCOs can be digitally tuned
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top