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Getting inside the SiP

Posted: 01 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:design? sip? soc? ic? dram?

Many design teams are taking a harder look at the system-in-package (SiP) alternative to conventional SoC design as the advantages of combining multiple dice into one package have been well-documented. The approach exploits the low cost and rigorous testing of commodity ICs like DRAMs. It also allows specialized circuitry to reside on its own dice, can integrate high-quality passive components into the package and can reduce design risk and shorten time to volume production compared with a complex SoC design. Finally, it can lever IC designs that are already in production, well up the yield curve and field tested.

But combining several dice into one package is not simply a matter of ordering a different package option from the assembly vendor. For starters, there is the decision about how to arrange the dice. The obvious approach is to mount the dice side by side on a substrate, but then there is the matter of right side up with wire-bond interconnect, flip-chip with solder bumps to pads and traces on the substrate, or some hybrid method.

Or, the dice could be stacked. But this just leads to more questions: How do you stack them? Use distribution layers between the dice to reroute signals? Use one stack or multiple stacks growing up from one large die? Wire bond between the dice? However these decisions are resolved, the problem remains of modeling and analyzing the interconnect environment. This must be done at least as carefully for the connections inside the SiP as it would be done for interchip connections on a board.

And there are exciting new possibilities. Dice can be given new layouts with the I/O pad locations optimized for the SiP to shorten wire length or to make flip-chip connections possible. Wire bonders can be designed to strictly control not just the length but also the shape of bonding wires to precisely control inductance. Strength of pad drivers can be reduced because of the reduced loads inside the SiP, improving signal integrity and slashing energy consumption.

This is just the beginning of the SiP story, and we are happy to bring you an introduction to it.

- Ron Wilson

EE Times

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