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Agilent proves 6.25Gbps serdes core in 90nm process

Posted: 06 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:agilent technologies? 90nm? cmos? asic chip?

Agilent Technologies Inc. has announced that it has validated its third-generation SerDes core in a 90nm CMOS process technology, making it possible for OEMs to embed as many SerDes channels (each operating at up to 6.25Gbps) as needed onto a single ASIC chip.

In tests conducted at Agilent, the embedded SerDes ASIC achieved error-free transmission driving signals over FR4 material a distance of 76 centimeters (30 inches) using two connectors.

The 90nm SerDes core is compliant with Ethernet XAUI and has features such as 1149.6 AC-Extest to test AC-coupled connections between ICs on the PCB, an LC-based oscillator, decision feedback equalization, and internal 100-ohm differential termination. The core also provides automatic receiver DFE tuning, BERT on chip for channel optimization, and a low bit error rate of

Agilent's embedded SerDes ASIC development model incorporates testing capabilities as early as the definition of system-level architecture and accounts for in-circuit manufacturing test, function test, system turn-on and debug, and field diagnostics.

- EE Times





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