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Altera unveils unified design flow

Posted: 08 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:powerplay altera quartus? IC design software? early power estimator?

The balance between speed and power. This is what the new version of Altera Corp.'s Quartus II design software promises to offer.

Today, the company announced that it is shipping v4.2 of its Quartus II design software, which it claims is the industry's first and only design tool to offer a unified design flow for the development of FPGAs, CPLDs and structured ASICs.

"Because of the advancements in semiconductor and architecture, we need a chip that engineers can put a whole system in," said Louie Leung, Marketing Director for Altera Asia-Pacific. "Quartus II is a tool that deals with 90nm power performance challenge. We are looking at a powerful desktop tool that can deliver power EDA capability. It is a software that people can use to design logic and system on a desktop," he added.

The power tools
With the latest version of the Quartus II software, Altera introduces the PowerPlay technology suite, an advance tool for programmable logic power analysis and optimization. This suite of tools will allow designers to analyze the power consumption of their Altera CPLD, FPGA or structured ASICs designs, and to perform automated control and optimization of this power consumption, the press release said.

There are two analysis tools included in the PowerPlay suite: the PowerPlay Early Power Estimator spreadsheet and the PowerPlay Analyzer tool.

The PowerPlay Early Estimator spreadsheet can be downloaded free from the company's website, and works together with the new version of Quartus II to provide power consumption estimates early in the design cycle. During the implementation phase, the PowerPlay Power Analyzer tool can then be used to refine power estimations. This tool improves estimation accuracy by combining an advanced "vectorless power analysis" algorithm with place-and-route results, Altera added.

In addition to the new PowerPlay technology, v4.2 also includes over 100 new features and enhancements. New additions include an implementation and timing analysis feature that analyzes and controls clock skew and data skew, allowing designers to model clock jitter and enable better analysis and optimization of register control signals.

Meanwhile, the enhanced SOPC (System on a Programmable Chip) Builder multi-clock domain support includes new features to support integration of systems with components operating in multiple clock domains.

"The SOPC Builder is actually a subsystem development tool. In the beginning, it was developed for our Nios processor," explained Leung. "But we now enhanced SOPC Builder in such a way that it helps the designer to develop whole subsystems into the silicon."

The third new highlight of v4.2 is the RTL-to-gates formal verification feature that supports new RTL-to-gates functional equivalency checking with the Cadence Conformal LEC formal verification software.

Speed/power balancing act
Throughout 2005, additional features will be added to the PowerPlay suite, including automated optimization tools. According to Altera, these PowerPlay Power Optimization tools will provide designers with an efficient, automated way to optimize power consumption in FPGA, CPLD and structured ASIC designs.

Leung said that when 90nm was talked about in the past, people looked at it in one dimensionhow to optimize speed. "Then, even by optimizing speed, you don't actually compromise your power performance significantly. But now it's a different ball game. The designer now has to look at both speed and power at the same time," he added.

Version 4.2 of the Quartus II software is available for Windows XP (including service pack 2), 2000 and NT; Solaris 8 and 9; Red Hat Linux 7.3, 8.0 and Enterprise 3.0 WS; and HP-UX 11.0. Both the subscription edition and the web edition of Quartus II v4.2 are available. The subscription edition is now shipping to all customers with an active software subscription, while the web edition is available free by download or from the web edition software suite CD. Annual subscription for the design software is $2,000 for a node-locked PC license.

- Margarette Teodosio
Electronic Engineering Times-Asia




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