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Mentor adds more functions to Calibre platform

Posted: 15 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:mentor graphics? caliber? design-to silicon platform? calibre transition? measure and analyze?

Mentor Graphics Corp. recently announced additional functionality for its Calibre design-to-silicon platform in the form of Calibre Transition, Measure and Analyze to address critical design for manufacturing (dfm) requirements.

According to the press release, the Calibre design-to-silicon platform is a comprehensive set of tools addressing the complex handoff between design and manufacturing. The cornerstone of the Calibre design-to-silicon platform is a single, robust hierarchical data processing engine that allows for the essential interaction and data sharing required between all tools in the platform, said Mentor.

"Design for manufacturing is nothing new, but the degree to which nanometer technologies have created additional yield considerations is unprecedented," said Joe Sawicki, VP and GM for the company's design-to-silicon division. "Over the last several years, manufacturing for design, primarily resolution enhancement technology, has been the key to ensuring yield. Now, achieving yield is requiring the EDA industry to pioneer new technology, make significant changes to existing tools, and provide a more robust communication link between design and manufacturing."

The design-to-silicon platform has been extended to include functionality to address a variety of DFM requirements. To assess yield loss due to via failures, the functionality in DFM Transition allows users to identify via transitions by layer and via count, analyze relevant via statistics, determine layout quality and automatically insert vias where needed. To account for and accommodate new foundry DFM rules, the functionality in DFM Measure helps determine to what degree a design adheres to foundry 'recommended' DFM rules, and presents statistics on adherence for the whole chip, by area and by cell. The DFM Measure also enables users to visualize layout features by DFM rule priority, histograms and color maps through Calibre RVE (Results Viewing Environment). Meanwhile, the DFM Analyze combines DFM rule priority and degree of severity with statistical occurrence information by region or cell.

Mentor said they are currently working with advanced customers on additional DFM capabilities that address areas such as litho verification, a technology that will show designers how the intrinsic fluctuations of the manufacturing process can distort the layout's final image. Another area of on-going development is feature yield analysis, a capability that identifies which features are most inclined to be at risk of failure, assesses the relative impact of the risk, and helps designers use that information to develop more robust design and feature-aware Test methodologies.

Presently, the company is preparing to introduce the Manufacturing Integration Initiative (MII), in which the Calibre design-to-silicon platform can be leveraged by mask and wafer inspection equipment to guide a more proactive and judicious metrology scheme, based on a sophisticated understanding of the chip layout, and its interaction with the process.

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