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Interconnect variation: Garbage in, out

Posted: 16 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:chemical mechanical planarization? cmp? rcl? interconnect? copper density?

Smith: The accuracy of the extracted parameters is only as good as the accuracy of the data that is input to the extraction.

The transition to copper and 90nm process nodes has raised the specter of increased interconnect process variation. Physical variations in copper interconnect lead to interconnect electrical-parameter (RCL) variation, which creates more potential variation in the actual performance and power consumption of the chip.

The ideal solution is to eliminate first the process variation. Improvements in chemical mechanical planarization processes and the introduction of dummy fill/slotting into layouts are being implemented with improved results, but interconnect variation persists. Unique interconnect patterns for each design, an increasing number of metal layers and decreasing line widths have conspired to force designers to accept interconnect variation.

The primary method employed to do this today is to assume "worst-case" variation, where worst-case electrical parameters are extracted and used at multiple points in the design process. This approach treats variability as uncertainty, and hence forces designers to create very conservative designs. Designers are typically not aware of this worst-case scenario, since EDA tools automatically use worst-case electrical parameters.

Perhaps the most important tool in the critical path of this process is parameter extraction. Extraction tools such as Raphael, Star RCXT, QuickCap, Fire and Ice QX, Assura RCX, Calibre xRC and Netan take a physical description of the interconnect in the layout; convert that into resistance, capacitance and inductance on wires; and feed the information into various design and verification tools. A plethora of alternatives is offered, from 2D to 3D field solverswhich can, at the high end, precisely extract resistance, capacitance and inductance with greater than 99 percent accuracy. There is usually a trade-off between speed and accuracy.

The flaw in this process is that the accuracy of the physical-design description that is input into the extraction tool depends on the manufacturing processand not all manufacturing processes are equal.

Some progress has been made by adding basic intelligence to the physical interconnect data interpretation by extraction tools. The most common approach is to use a "density" model as a proxy for the thickness variation across the chipwith the assumption that uniform copper density will result in one copper thickness. This same proxy can also be used as a design rule in the place-and-route tool. The density models have even been extended with "range of influence" weighting, as well as rules for line width and spacing.

But the accuracy of the extracted parameters (and hence performance) is only as good as the accuracy of the data that is input to the extraction: Garbage in, garbage out. The solution is to provide as-manufactured thickness for all the interconnects on the chip. The virtual-manufacturing process would not only predict the actual variation but could also represent a specific foundry's process.

The virtual-manufacturing transformation could be done in hours, instead of weeks, while the chips are manufactured and measured. These manufacturing-aware designs would result in higher performance, lower power consumption or higher yields.

An accurate virtual-manufacturing capability is underway and is close to becoming a reality. We could soon eliminate the garbage.

Taber Smith
President and CEO
Praesagus Inc.

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