TSMC, NEC, Renesas, Toshiba describe novel MRAM cells

At the International Electron Devices Meeting (IEDM) here this week, NEC, Renesas, TSMC and Toshiba are expected to describe competitive cell structures for new and emerging MRAM devices.

There appears to be two types of cell flavors for MRAMs -- FET and cross point. So far, the world's highest-density MRAM is a 16-megabit device based on an FET cell. In MRAMs, the data is stored in the orientation of the magnetization of the storage layer.

In one paper at IEDM, Taiwan Semiconductor Mfg Co. Ltd (TSMC), the Electronic Research and Service Organization (ERSO) in Taiwan and others provided more details about its collective efforts in MRAM technology.

The silicon foundry giant claims to have developed novel MRAM structures based on a 0.18-micron process and a pillar write word line (PWWL) cell. The company proposes to shrink the bit size by a "so-called ExtVia process" while reducing the writing current by a factor of two, according to the paper.

In a different approach, Toshiba Corp. and NEC Corp. of Japan jointly presented a paper on a low-power 6F² MRAM based on a cross-point cell. The 1-megabit MRAM chip is said to have been manufactured in a 130nm process and a 0.24 x 0.48-?m² magnetic tunnel junction technology, according to the paper.

The chip is said to have a 250nm access time and 1.5V operations. "To suppress the sneak current, a cell design is proposed for the new (cross-point) cell with a hierarchical bit line architecture," according to the paper.

Japan's Renesas Technology Corp. claims to have fabricated an MRAM for high-speed operations beyond 143MHz. In a paper at IEDM, Renesas made the chip by using a 130nm technology, with a four-level copper damascene process, "We adopt 1T-1MTJ (1-transistor-1MTJ) type MRAM, which is good high-speed read operation in comparison with cross-point type MRAM," according to the paper.

- Mark LaPedus

Silicon Strategies