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Agilent, Synopsys partner on scan diagnostics methodology

Posted: 20 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:agilent technologies? synopsys? diagnostics reference methodology? 93000? smartest program generator?

Agilent Technologies Inc. and Synopsys Inc. announced a scan diagnostics reference methodology that promises to speed fault localization and failure analysis for semiconductor design and test engineers faced with identifying device failures under increased time-to-market pressure.

A result of the companies' three-year alliance, the methodology is enabled by Agilent's 93000 SmarTest Program Generator (pg) 2.2 and Synopsys' tetramax automatic test pattern generation (ATPG) solution, in conjunction with Agilent's 93000 SoC series test platform. This combination of tools automates the bidirectional information sharing between EDA and automatic test equipment (ATE) required for scan diagnostics.

As process geometries shrink and device complexity grows, identifying device failures becomes increasingly difficult, explained the two companies. The demand for shorter time-to-market and lower product cost makes rapid diagnostics and fault localization vital during the first silicon evaluation and production ramp up. EDA companies have begun to offer fault localization tools, but they require failure information from automatic test equipment. Until now, a standardized and supported means for sharing information from ATE has not been available, according to the press release.

"Our customers want us to link design and test more closely in order to lower the overall cost of test," said Tom Newsom, VP and GM of Agilent's SoC Business Unit. "Our strategic alliance with Synopsys has successfully contributed toward bridging the gap between EDA and ATE."

The 93000 SmarTest PG 2.2 offers a seamless transition from the EDA environment to the capabilities of the Agilent 93000 SoC series, which speeds test development for functional and scan tests. It provides a scan failure map for viewing scan failures on the Agilent 93000 SoC series in their native scan context, speeding first silicon debug. In addition, it features a simplified user interface and command-line operation, and supports industry-standard EDA input formats, including Standard Test Interface Language (STIL), Waveform Generation Language (WGL), Value Change Dump (VCD), Extended VCD (EVCD) and Core Test Language (CTL).

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