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Toshiba supports Cadence RTL compiler for ASIC design

Posted: 21 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:taec? encounter rtl compiler synthesis? asic? soc?

Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis. The new kit supports designs for implementing in TC280 (130nm), TC300 (90nm) and newer process technologies.

"We have successfully used SoC Encounter for the past two years to take complex custom designs into production," said Shigenori Imazato, VP of engineering for TAEC Design Centers. "These have mostly been at TC280 (130nm) technology level. By adopting Encounter RTL Compiler in addition to SoC Encounter, we have realized a consistent, streamlined flow from RTL-to-GDS. By using the Cadence SoC Encounter RTL-to-GDS flow, we can achieve better performance and faster turnaround time," Imazato added.

"TAEC has been a long-time user of Encounter RTL Compiler, beginning with its successful use on the world's fastest synthesizable 64bit MIPs core in 2002," stated Chi-Ping Hsu, corporate VP, synthesis solutions, Cadence. "An increasing number of Custom SoC/ASIC vendors such as TAEC are selecting Encounter RTL Compiler as the final synthesis tool in their signoff flow because of its proven ability to increase chip performance, speed turnaround time and produce higher Quality of Silicon (QoS)," Hsu added.





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