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STMicro has full 65nm IC, offers 65nm design platform

Posted: 21 Dec 2004 ?? ?Print Version ?Bookmark and Share

Keywords:65nm? cmos design? soc?

STMicroelectronics said Dec. 16 that it has completed the design, and tape-out, of a complex IC that demonstrates its 65nm manufacturing process technology. The company also said it is also ready to deliver a 65nm CMOS design platform to internal design teams and those of customers allowing them to start developing next-generation system-on-chip (SoC) products.

ST did not say what type or complexity of chip had been made using the 65nm process or how soon it expected more designs to tape-out for implementation in the 65nm process. Nor was there any mention of where Freescale Semiconductor and Philips Semiconductor, ST's partners in the Crolles2 Alliance, stand with offering 65nm design and manufacturing capability.

ST's 65nm library includes multiple process options allowing cells to be optimized for high performance, low power, or general-purpose use. Each option shrinks 90nm products by half while improving speed up to 30 percent or reducing leakage by half in operation.

The platform offers two standard cell libraries, optimized for performance and density, which include multiple voltage I/O cells; multiple memories; and analog IP (intellectual property). The cells support densities of more than 800,000 gates per square millimeter and a core supply of 1.0V or 1.2V, with metal pitches of 0.20?m and from six to ten metal routing layers.

"Being the first to deliver a 65nm design platform validates our alliance strategy, in general, and the efforts of the Crolles2 Alliance, in particular," said Didier Chapuis, group vice president, platform development at STMicroelectronics, in a statement.

Further extensions to the initial platform offering, including SOI (silicon-on-insulator) versions and high-performance integrated passive devices, are in development and are set to become available soon, ST said.

The Crolles2 Alliance comprises STMicroelectronics, Freescale Semiconductor, and Philips Semiconductors, and the alliance can supply services to ease the adoption of 65-nm process technology, ST said.

Crolles2 can provide a prototyping respin cycle time of less than one week for 130nm ICs together with mask set cost reduction and the use of e-beam technology. Crolles has also scheduled a multi-project reticle service has started for 65nm designs, allowing multiple customers to share mask costs.

EDA tools from Cadence, Mentor Graphics, and Synopsys support the 65nm design platform, ST said.

- Peter Clarke

Silicon Strategies





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